Design And Verification Of Solid-state Disk Master Chip Test System Based On 93K Platform

Under the trend of modern digital life,the amount of data shows an exponential growth,which puts forward higher requirements for data storage media in terms of speed,capacity,and reliability.The solid-state drive(SSD)adopts the semiconductor memory chip structure of "flash medium and main control".The main control chip undertakes the functions of command,calculation and coordination,which directly determines the performance of SSD in all aspects.Various usage scenarios put forward higher requirements for SSD main control chips,and also raise higher request to related product testing.When testing at high temperature,the leakage current and power consumption of the main control chip will increase.When the heat caused by abnormal power consumption in the chip is accumulated in the chip,it will further cause the chip to work in an unstable state,This leads to nonlinear distortion of test data.In addition,problems such as data distortion and low yield caused by the wafer area temperature difference,pin card deformation,and uneven depth of pin marks caused by environmental factors have become the difficulties of current high-temperature testing.On the basis of studying the SSD main control chip test,this paper optimizes the configuration for test-related software and hardware with the high temperature test,nd conducts the high temperature environment CP test of the SSD main control chip based on Advan’s 93 K test platform.The main work includes:(1)Study the conversion principle of test vector to pattern,which involves many file formats and related configurations,which makes the vector generation process more complicated,the generated vector is difficult to modify and the execution efficiency is low.This affects the test code development and debugging cycle.In response to this problem,the vector data format is designed according to the characteristics of vector writing,and an optimization scheme for vector generation based on SPI protocol is designed and implemented.Compared with the original test scheme,the read and write efficiency of registers is increased by 60% and 71% respectively,and the MBIST test time was reduced38.04%,Scan test time was reduced by 31.54%,and the overall test time was reduced by30.27%,which met the test plan design requirements.(2)Research on the accuracy and precision of the existing Prober probe station temperature control system cannot meet the high temperature test requirements,which is mainly manifested in the large difference between the overall temperature of the wafer after heating and the test set temperature,and the existence of areas in the wafer.The temperature difference causes the actual test temperature of the wafer to fail to meet the test requirements.In response to this problem,it is proposed to improve and optimize the configuration of the temperature control system based on the product test temperature requirements,so that the temperature difference between the wafer and the test environment is within ±1.5°C of the product test requirements,and a probe card is designed and manufactured according to the test requirements of high temperature.Under the optimized solution test,the DUT works in a stable state,and the data is distributed evenly.The leakage current of the VCCK pin is concentrated between 0.0015～0.0025 A,and the OS test data is evenly distributed between 0.25～0.3A,which is consistent with the change of chip characteristics under high temperature.Meet the chip testing needs.(3)This paper focuses on completing the SSD main control chip test in a high temperature environment,mainly for the three types of tests of SSD main control chip,DC Test,AC Test and Function Test,reasonably planning the Test Flow and designing the test results to be divided into Bin items.Module optimization for SSD main control chips test: First,add LDO calibration test to the measurement LDO test item,obtain the closest expected calibration value in the current environment,and perform programming for chip self-error repair.Second,increase the OSC calibration test,get its frequency offset,and perform self-repair and burn.Third,focus on the stability of the test at high temperature,and test the control circuit under various signal strengths.Research and design the test program on the 93 K platform,and perform the CP test on the selected DUT.Among them,the LDO test result is 1.8～1.9V,the total current of the leakage test is 0.0025～0.0035 A,the data distribution is uniform,close to the upper limit of the DUT design index,in line with the change of the DUT operating characteristics under high temperature,the test time is reduced by 30.27%,and the AC type test time is reduced More than 30%,to meet the design requirements.