Research On Surge Protection Of High-speed Interface And Simulation Design Of TVS Array

With the continuous development of the integrated circuit industry,more and more high-speed data interfaces are used in consumer digital products to achieve fast synchronization and real-time transmission.However,qualified surge protection devices,such as TVS and TVS arrays,are needed to be connected to high-speed data interfaces due to its poor ESD protection capabilities.At the same time,the data transmission process of the high-speed interface cannot be affected by the TVS array applied to the high-speed interface,so an extremely low junction capacitance and latch-up immunity are required.Based on the above content,this thesis conducts research and simulation design of TVS array for surge protection of USB and HDMI.The specific works of this thesis are as follows:1.The classification of surge,the role of TVS devices on high-speed interfaces,and the history and current status of research on electrostatic protection at home and abroad are introduced.2.First of all,the TVS protection principle,the structure and working process of the TVS array are descripted.Then the discharge model and test model for evaluating the ESD protection capability of the device are mentioned.Furthermore,three requirements of the high-speed data interface for TVS arrays are proposed and further explained.Finally,the model used in the simulation and the multi-pulse TLP simulation are given,which points out the direction for evaluating the ESD protection capability of the simulated TVS array.3.The steering diode is designed separately from the SCR-type core protection device.Referring to various existing structures for reducing the trigger voltage and their advantages and disadvantages,combined with the electrical characteristics,the Zenerassisted trigger SCR is adopted.Then the design of latch-up free is optimized by adopting the reducing bipolar gain and shunt the SCR current at the same time.The holding voltage has been effectively increased.Finally,the sectional view of the steering diode is given,and the improved four channel,low capacitance,low trigger voltage,and high holding voltage TVS array structure is proposed.4.The improved TVS array is simulated by Senaturus Process,combined with the structure and electrical characteristics of the device,the process parameters are biased,and the optimal value is determined by comparing the simulation results.Then cosimulation of steering diodes and the SCR-type core protection device is performed through circuit connections,and the multi-pulse TLP simulation test and layout drawing of the TVS array are carried out.The simulation test results show that the designed fourchannel TVS array has a trigger voltage of 6.89 V,a trigger current of 10 m A,a holding voltage of 5.52 V,a junction capacitance of 0.3 p F,a clamping voltage of 12.41 V when the TLP current is 16 A,and the level 4 protection capability of IEC61000-4-2.In this thesis,through the analysis and comparison of existing structures,simulation improvement,process verification,and bias optimization,all the electrical characteristics have been completed.The designed TVS array has certain reference value for the latchup immunity design of on-chip ESD protection and off-chip TVS design.