Study Of High Voltage ESD Characteristic Of Substrate Trigger SCR-IDMOS Stacking Structure

Electrostatic discharge(ESD) is one of the most important reliability problems in IC industry, every year nearly 40% of the invalid IC is caused by ESD/EOS(electrical overstress).With the development of semiconductor technology, Especially the widespread application of high voltage intelligent power technology, high voltage ESD problem of IC chip is more and more serious. Low holding voltage is the most prominent problem of high voltage ESD, If ESD occurs when the protected chip is powered, latchup will be triggered easily.First, this paper introduces the basic working principle of ESD and several familiar ESD device, discusses CMOS latchup、the parameters of influencing CMOS latchup and the relationship and distinguish between latchup and ESD, analyzes the latchup of high voltage ESD problems, points out that improving holding voltage is the most effective way to solve latchup, and gives several method and case of improving holding voltage.Secondly, this paper proposes a novel self-triggering STSCR-LDMOS(substrate trigger semiconductor control rectifier-laterally diffused metal oxide semiconductor) stacking structure which is applied in high voltage ESD, and uses the simulation method of multiple Pulse TLP(transmission line pulse) simulate and analysis the structure. Analysis results show that the holding voltgage of STSCR-LDMOS stacking structure increases with the number of stacking structure, however, the trigger voltage depends mainly on the trigger voltage of STSCR-LDMOS1. for example, when the trigger resistance is 100 Ω and the stacking number increases from 1 to 4, the holding voltage increases from 6.9 V to 25.4 V, however the trigger voltage increases merely from 71.6 V to 79.7 V. this paper also analyzes the influence of the distance L between N+ and P+ of STSCR-LDMOS cathode、the distance L0 between P-trig and N+ and trigger resistance on the holding voltage and the trigger voltage of stacking structure, and gives the best value of the distance L、L0 and trigger resistance.Finally, this paper proposes a LDMOS trigger STSCR-LDMOS stacking structure, which is optimization structure of self-triggering STSCR-LDMOS stacking structure. The simulation analysis shows that LDMOS trigger STSCR-LDMOS stacking structure has a smaller trigger voltage. Therefore, in order to obtain higher holding voltage we can stack more STSCR-LDMOS unit. For example, when the trigger resistance is 50 Ω and stacking number increases from 1 to 6, the holding voltage increases from 7.4V to 40.5V, and the trigger voltage increases only from 70 V to 75.3V.