Investigation Into High Holding Voltage Of Bidirectional SCR ESD Device Structures And Performances

In the manufacturing,packaging,transportation and use of integrated circuits,the accumulation and release of electrostatic is inevitable,which is the key factor affecting the reliability of integrated circuits.Therefore,electrostatic protection is an important part of chip design.This paper focuses on the structure and performance of dual-direction Silicon Controlled Rectifier(DDSCR)electrostatic protection devices.The purpose is to design a new DDSCR device with better comprehensive performance for 20 V and 70 V applications.The new device was analyzed theoretically and simulated by Technology Computer Aided Design(TCAD),fabricated and tested in 0.18 μm BCD process.The specific research content is as follows:(1)An HVDDSCR＿FP device applied to CAN bus is proposed.By introducing floating P+,the device can increase the holding voltage from 12 V to 20 V and the failure current from 5 A to 35 A at positive and reverse 25 V trigger voltages.This structure not only has symmetrical positive and reverse I-V characteristic curves,but also has the characteristics of high holding voltage and good robustness.The paper also discusses the influence of the width of the N-type isolation well on the performance of the device and the reasons.After optimization,the leakage current of the device is reduced from the μA level to the n A level.(2)The structure of HVDDSCR＿HFP device is changed horizontally,and HVDDSCR＿HVNW device and HVDDSCR＿PW device are proposed for 70 V application.The test results show that the holding voltage of HVDDSCR＿HVNW device is about 30 V,and the positive and reverse failure currents are increased from6.68 A and 7.07 A to 31.9 A and 28.36 A,respectively.In order to study the effect of PW level indent on the electrostatic performance of HVDDSCR＿HFP device,HVDDSCR＿PW device was proposed.Compared with the reference device,the positive and reverse holding voltages decreased,but the positive and reverse failure currents increased from 6.68 A and 7.07 A to 18.22 A and 9.92 A,respectively.High protection level can be achieved without increasing device area.(3)The structure of HVDDSCR＿HFP device is longitudinally changed,and HVDDSCR＿PDT device and HVDDSCR＿PBL device are proposed for 70 V application.For HVDDSCR＿PDT device,the reasons why the device performance could not be improved were analyzed from the three aspects of PDT layer concentration,PDT layer depth and inserted PDT lateral size.For HVDDSCR＿PBL device,because the added PBL layer is in a deep position inside the device,it has little influence on the lateral parasitic transistor.Meanwhile,the added PBL layer inside the device can improve the base concentration of the vertical parasitic transistor,make the device easier to open,and effectively prevent TLP curve jitter.However,as the discharge path of electrostatic does not change after opening,the electrostatic performance parameters of the device cannot be improved.