Design Of ESD Protection Devices For Integrated Circuit Based On LVTSCR

Electro Static Discharge(ESD)has become a main reason for the failure of integrated circuit products.With the advancement of process technology,the feature size of the device is getting smaller and smaller,the chip's anti-ESD ability is also declining,and the on-chip ESD protection circuit has been become an indispensable important module in circuit design.The ESD protection device is the most basic unit of the protection circuit.Due to the continuous decline of the process feature size,the ESD design window is compressed.The trigger voltage and the holding voltage of the ESD protection device have become the focus of device optimization.In view of this,the main goal of this article is to design ESD protection devices with high holding voltage and low trigger voltage.This article is based on the 0.18?m BCD process.After comparing the advantages and disadvantages of traditional ESD protection devices,the traditional LVTSCR is used as the optimal design object.The main innovations are as follows:1.In view of the shortcomings of low holding voltage of the traditional LVTSCR,this paper proposes a new type of EW-LVTSCR.By adding a heavily doped P-type shallow well below the MOS structure,the amplification factor of the parasitic NPN transistor is reduced,and the positive feedback mechanism inside the device is weakened,thereby achieving the purpose of improving the holding voltage.Using TCAD simulation tools to verify,the experimental results show that: after adding the P shallow well,the holding voltage of the device increased significantly,gradually increasing the lateral size of the P shallow well,the holding voltage of the device can increased to more than 3.8V,which can solve latching problems in the 3.3V protection circuit.In order to expand the scope of application of the new device and change the position of the P shallow well,with the trigger voltage slightly increased,the holeding voltage of new EW-LVTSCR2 above 5.8V and can be used in the 5V protection circuit.2.In order to reduce the trigger voltage of the device,starting from the idea of reducing the voltage consumption on the trigger path,this paper proposes a MTSCR device structure that reduces the voltage consumption on the trigger path after the device avalanche breakdown,thereby reducing the trigger voltage.The experimental results show that the avalanche breakdown voltage is unchanged basically,and the trigger voltage drops by 0.5V.The EW-MTSCR structure embedded in the P shallow well achieves the design goals of low trigger voltage and high holding voltage.On the premise of holding voltage meets the requirements of the 5V protection circuit,the current after the GGNMOS path turned on is introduce into the well in EW-LVTSCR3 device structure.Not only is the SCR path easier to turn on,but the trigger voltage is reduced by 0.6V.