Design Of Silicon Controlled Rectifier Electrostatic Protection Device For Low Voltage CMOS Process

With the continuous development of integrated circuits,static electricity has become a key factor affecting the reliability of integrated circuits.The static electricity,which appears during the testing packaging,and transportation of integrated circuits,is threatening the chp's reliability,security and stability.According to statistics data from National Semiconductor,chip failure due to electro-static discharge(ESD)accounted for 58%of the total IC failures.Therefore,the electrostatic protection of the chip has become a focus for domestic and foreign researchers.Common ESD protection devices include diodes,MOS,and SCR.In the low-voltage CMOS process,the diodes take up too much layout area and the overall ESD performance is poor.The MOS transistors have low robustness and small unit-area-failure current.The SCR device has a higher robustness,a smaller layout area,and a lower parasitic capacitance,which has been widely used.However,the SCR device has the disadvantages of too high trigger voltage and low holding voltage at the same time.To address these shortcomings,research at home and abroad is mainly carried out from the perspectives of optimizing the device structure,changing the trigger mode,and implementing the layout,such as MLSCR and substrate triggering technology.This article designs and optimizes SCR devices in 0.18um CMOS process.The specific tasks are as follows:(1)An LVTSCR structure with a built-in diode string is designed.Firstly,the traditional SCR device ESD performance was simulated and tested.The TLP testing result shows that the trigger voltage of traditional SCR devices is as high as 18.89V,while the holding voltage is only 3.83 V,which does not meet the requirement of 5V operating voltage.For excessive big trigger voltage,LVTSCR brings down the trigger voltage by increasing the doping concentration of the trigger surface,and the trigger voltage is reduced from 18.89V to 12.23V.For excessive small holding voltage,a novel LVTSCR structure with built-in diode strings is designed to elevate the holding voltage to 5.20V,which satisfies the requirement of 5V working voltage.(2)Performance analysis and structure optimization of DDSCR devices from both device layout and structure perspectives.A.There are few studies on the influence of DDSCR layout on device performance in the existing literatures.In this paper,three different layout implementations of finger DDSCR,snake-type DDSCR,and track-type DDSCR are designed,and their ESD performance are compared by a figure of merit(FOM),the finger DDSCR has the highest FOM of 2.539.B.The traditional DDSCR device's structure has been optimized,and the P+/N+ doped regions of anode and cathode are arranged in a segmentation way,which elevates the holding voltage by reducing the emitter injection efficiency of the parasitic triode in the DDSCR.The TLP testing results have shown that the optimized device's trigger voltage is 12.6V,and the holding voltage is 6.91V,which meets the requirement of 5V working voltage and reducing the layout area.