Surface Current Reduced Model And Device Of High Voltage ESD Protection In Power Integrated Circuits

In integrated smart power application, the robustness of ESD (Electro-StaticDischarge) is one of determining factors for stability and reliability of the system. Withstronger ESD robustness, the design cycle and design cost of HV （high Voltage）power IC can be cut down. Therefore, it’s very important and useful to study theworking mechanisms of the ESD protection devices and improve their protectionabilities. However, surface current integration easily occurs with high voltage and highelectric field, and worsens the lattice temperature, rises up leakage current, andincreases the discharge resistance. Therefore, A series of HV ESD protection deviceshave been designed and optimized at home and abroad to optimize the discharge path,and improve the discharge ability.However, the characteristics of HV ESD protection devices are sensitive withmanufactory process parameters, and the optimize methods for one process may notavailable for other processes. It’s very hard to set up a universality theory for ESDrobustness optimization. Meanwhile, the modification of manufactory process willlower down the compatibility and increase the cost.In this thesis, the surface current integration problem is studied, and the main workis as follows.1. Surface current reduce model is proposed. The problems caused by surfacecurrent integration are studied. Based on the temperature distribution andelectro-thermal model, the lattice temperature increasing and the hot pot problem withsurface current integration are analyzed. Based on the surface tunnel model, therelationship between leakage current and surface current integration is discussed.Meanwhile, the discharge resistance increasing problem with surface current integrationis studied. By summarizing the mechanisms of surface current integration, twotechniques are proposed: surface generated current restrain technique and surfacetransport current restrain technique.2. Based on the surface current reduce model and techniques, settle differentproblems for devices under ESD stress.(1) Surface generated current restrain technique is realized by restraining thesurface electric field and surface impact ionization generation rate, or by enhance the current gain of the parasitic devices to reduce the avalanche multiple currentcomponent.Based on the surface generated current restrain technique, soft leakage problem of20V LDMOS with epitaxial process is settled. The mechanisms of soft leakage underlow level ESD stress is analyzed with electric field induce and thermal induce. Theexperiment confirms that, for20V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA or even0.05nA, and the second breakdown currentincreases from2.2A to4.0A; for40V LDMOS, the leakage current of the optimizedstructures keeps consistent at1nA, and the second breakdown current increases from1.17A to1.62A.The influences of parasitic bulk resistance are discussed. Besides reducing oftrigger voltage, larger bulk resistance can restrain the surface generated current byincreasing the current gain of parasitic NPN. The bulk parasitic resistances arecalculated with geometric parameter. The experiment confirms that, the device withsegmentation P+implant has best ESD discharge ability, whose second breakdowncurrent increases from1.0A to1.88A.(2) Surface transport current restrain technique is realized by shunting the lateralcurrent component through the parasitic vertical devices, or by pushing the carriers deepinto the device body.The mechanism of strong snapback of700V LDMOS with bulk-silicon process isstudied. Based on surface transport current reduce technique, a parasitic vertical PNP isinduced in the novel structure to shunt the lateral part current. As the simulation results,the triggering of parasitic lateral NPN is restrained, and the novel structure has twiceESD discharge ability compared with the conventional one.Power clamp ESD protection of190V SOI PDP scan driver IC is studied. Based onthe surface current reduce model, the deep discharge LIGBT is used to replace theconventional HV Diode. With the parasitic PNP to reduce the avalanche currentcomponent, the surface generated current is reduced; with holes instead of electros inthe drift region, the carriers are pushed deep into the device, and the surface transportcurrent is restrained. The experiment confirms that, the second breakdown voltage ofdeep discharge LIGBT is217V compared with the HV Diode of251V, and the secondbreakdown current is0.52A compared with the HV Diode of0.39A. The PDP scandriver IC with deep discharge LIGBT is tested with HBM standard, and it has8KV HBM ESD robustness.3. The double snapback characteristics of LDMOS-SCR with bulk-silicon processare studied. With the analysis of mechanism, a criterion is proposed for the secondsnapback. By reducing the second snapback current and voltage, better ESD dischargeability can be obtained. The experiment confirms that, the second breakdown current ofoptimized structure increases from0.57A to3.1A.