Design Of High Speed ADC Based On Flash-SAR Structure

With the development of integrated circuit industry,analog-to-digital converter（ADC）plays a more and more important role in electronic system.In order to achieve the goal of high speed,high precision and low power consumption,more and more new ADC structures are proposed by circuit designers,in which successive approximation（SAR）ADC is applied to multi digital analog hybrid integrated circuits as a representative.Flash successive approximation（flash SAR）hybrid structure ADC is a new structure combining Flash ADC and SAR ADC.It has both advantages and disadvantages,provides a new direction of ADC development,and has become a research hotspot at present.The thesis designed a single channel 12bits 400MHz flash SAR ADC for time interleaving.According to the modeling analysis,a“5+10”two-stage ADC structure is adopted.Low power comparator array design is adopted for the first stage flash ADC,split capacitor technology and segmented capacitor technology are introduced for the second stage SAR ADC,and interstage redundancy is added to reduce the offset error of the first stage comparator.In thesis,the circuit and layout design are completed under the 28nm CMOS process,and the pre-simulation and post-simulation are carried out through spectre to realize the performance requirements of a single channel of 12bit and 400MS/s.The final post simulation results show that under 1V power supply voltage,the input signal frequency is 190.625 MHz,the sampling frequency is 400MHz,SFDR is 77.79d B,SNDR is66.87d B,ENOB is 10.82bits,the power consumption is 5m W,Fo M is 7f J/conversion-step,and the single channel layout area is 0.104mm~2,the performance index meets the design requirements.