Key Research On Multichannel Time-interleaved Flash ADC

The ADC (analog-digital converter) has been increasingly used in the field of wirelesscommunication systems, acting as a connector between the analog and digital signals,whose performance has limited the overall system’s development. With the rapid expansionof4G communications network, the requirement for the sampling speed of the ADC hasnever been stricter. In order to break through the process limitations, we adopt thetime-interleaved structure for the ADC.A6-bit time-interleaved Flash ADC implemented in TSMC90nm process achieved anequivalent sampling rate of6GS/s, with a1.2V power supply. Analyzing both themismatch of time-interleaved structure and the no ideal factor for the single channel design,the mismatch of the sampling time has been mainly concerned. A combination ofsimulation and statistical calculations, the system clock was designed to escape the ADC’sperformance from the clock skew error. To improve the single-channel design, severalmethods have been put into effort, such as adding track and hold circuit to reduce the errordue to clock jitter, using multi-stage cascade structure to decrease the probability forcomparator being metastable, employing DAC trimming to correct the comparator’s offset.Besides, by joining four input NAND logic gate and one-hot code together, we reduced theerror rate effectively. And an optimization design for the overall design layout wascompleted. The measured SNR was35.97dB at6GS/s with a1.431GHz input. The designhas reached our expectations.