Research And Design Of All Digital Calibration Algorithm For Time-interleaved ADCs

High-speed and high-precision ADC, which is a bridge between analog domain and digital domain,has been a hotspot in the field of communication systems. With the rapid development of the process, various non-ideal effects severely limit the performance of monolithic ADC. Time interleaved analog-to-digital converter(time-interleaved ADC, TIADC) is an effective way to achieve high sampling rates,which uses multiple ADC parallel sampling operations. However, due to the existence of non-ideal factors such as manufacturing process deviation and sampling time deviation, there is a mismatch between the sub-channels of the time interleaving ADC,resulting in a decrease in the dynamic performance of the system, finally resulting in the system dynamic performance degradation.This thesis first analyzed the three main sources of channel mismatch errors and their impact on the performance of TIADC system. For the most difficult time error calibration, designed and achieved a digital calibration algorithm. The calibration algorithm contains the time error estimation algorithm based on cross correlation of channel signals and improved high order time error compensation algorithm based on Taylor series expansion,which can satisfy the effect calibration in the entire Nyquist frequency. The calibration algorithm forms a feedback loop, which can achieve real-time correcting of error. The entire calibration algorithm forms a loop,can achieve real-time error correction, and can be extended to any number of channels.To verlify the validity of the algorithm,a 12bit-1 GHz four-channel time-interleaved ADC calibration model was built with MATLAB/Simulink, when the normalized frequency of input signal was 0.4064, the simulation results showed that the effective number of bits (ENOB) improved from 4.84bits to 11.96bits, signal to noise ratio(SNR) promoted 42.9dB,proved the validity of the proposed calibration algorithm;then the RTL level designed of the calibration algorithm, existed code level calibration algorithm of behavior model by Verilog HDL, using Modelsim completed the function simulation of the calibration algorithm's Verilog code; and the code through Quartus II integrated and downloaded to the FPGA development board,completed the hardware implementation and verification of the calibration algorithm;finally, completed ASIC design of the calibration algorithm based on SMIC 0.18?m process, and produced a layout of the calibration algorithm, and the results of the multi-level verification of the calibration algorithm are compared and analyzed, and the validity of the calibration algorithm is further verified.