Design And Implementation Of An Acquisition System Based On Time-interleaved Sampling Method

Power analysis attack causes a tremendous threat to the security of crypto chip. The effective method of attacking is achieved through acquiring the transient power information of the crypto chip, thereby calculating the secrete key. In order to develop more on method of power analysis attack, this article focuses on the characteristics of crypto chip such as high frequency and small aspect ratio of the encryption part area. Here the article introduces a design of transient power information sampling system with both ultra high speed and high precision.Time interleaving sampling is a remarkable way of breaking through the speed bottleneck of today’s ADC technology, on the premise of high precision. It builds a parallel system of ADC chips with relative low speed and high precision, using the time interleaving technology.With emphasizes in solving the calibration problem of collection system channel mismatch error in time interleaving samples, the article purposes a calibration method using both frequency domain and time domain. This method improves the precision of channel mismatch error calibration through synchronizing on-board signal source, calibration source clock and sampling clock source; compensating error based on FARROW structure filter and other methods. Result from experiments shows: ADC with sampling frequency of 5GSPS, the SNR and SINAD after calibration increase almost 30%, SFDR increases nearly 60%. This result validates the effectiveness of the calibration method.Jitter from the sample clock has a baneful influence on the precision of time-interleaved sampling system. The article adopts a series of methods designated to lower clock jitter: clock source improvement, frequency distributor and band-pass filter application, clock link elements deduction, etc. With these methods we implemented a extremely low clock jitter generator circuit. Result from experiments shows that: when the circuit generates a clock of 2.5GHz, jitter from noise is only 89.0fs RMS, which fulfills the requirement of time-interleaved sampling system.With the foundation of previous development of ADC technology, our project team design and implement an acquisition system based on time-interleaved sampling method. The system is composed of six modules: analog signal input, clock generation and distribution, power management, analog digital conversion, data receiving buffer, and data process report. From the result of the functionality of the whole system, sampling precision reaches at least 8 bit, when sampling frequency reached 5GSPS.