Design Of Read And Write Control Of Ferroelectric Memory Based On I2C Interface

As a new type of non-volatile memory,ferroelectric memory has the advantages of low power consumption,high reliability,and high radiation tolerance.And FRAM has always been the focus of research in the field of memory.With the rapid development of portable devices such as wearables and the IOT,higher demands are placed on memory in terms of capacity,power consumption,and area.The commonly parallel interface ferroelectric memory has high requirements for circuit design due to the large number of pins and complex port processing.The I2 C serial interface is widely used because of its small number of ports and its convenience and flexibility.Based on the above reasons,in order to expand the application scope of ferroelectric memory,two kinds of ferroelectric memory chips based on I2 C interface were designed,which were respectively adapted to the fast mode and high-speed mode of the I2 C bus.The work of the thesis mainly includes the following contents:1.Firstly,based on the principle of I2 C bus,the electrical structure and communication protocol of I2 C bus were analyzed.A detailed description of the advantages of I2 C bus was made,such as simplicity,high efficiency,low power consumption,easy control,and isolation protection for memory.And by comparing the characteristics of three common interfaces of ferroelectric memory,parallel interface,SPI interface and I2 C interface,the advantages of I2 C interface circuit compared with the other two interfaces were further highlighted,which provided a theoretical basis for the main work of the thesis.2.Afterwards,the I2 C read-write working mode and other function timings were explained in detail,and two kinds of ferroelectric memory read and write circuits that could work in the I2 C bus fast mode(1Mbit/s)and high-speed mode(3.4Mbit/s)were completed by 0.13?m CMOS process.Control circuit design.Each circuit module in the corresponding I2 C interface chip were completed,including power-on reset circuit,I2 C state machine signal processing circuit,data latch circuit,address latch and self-add one circuit,memory interface enable circuit,etc.In addition,the unique manufacturer ID reading circuit design of the high-speed mode chip has been completed,and the overall circuit design has been optimized with the goal of low power consumption.3.Finally,the simulation verification of the read-write control circuit was completed.After the overall circuit was confirmed,the layout design was completed and physical verification was been carried out.Then the parasitic parameters were extracted,and the post-simulation verification was carried out,and the burr problem caused by the parasitic capacitance was improved by adding a deburring countermeasure circuit optimization design.The simulation results showed that the read-write control circuit could realize a variety of read-write operations of ferroelectric memory under voltages from 2.7v to3.65 v,temperatures from-55°C to 125°C and various process corners to ensure the stability of the circuit..The functions were correct and met the design requirements.