Studies On Key Technologies Of High Reliable Ferroelectric Memory Based On PZT Ferroelectric Film

Ferroelectric random access memory （FRAM） is a new semiconductor memory, inwhich ferroelectric material is integrated with conventional semiconductor technologyas storage dielectric. Because of the advantages of nonvolatile, low power consumption,fast access time, high endurance and high radiation tolerance, FRAM is regarded as oneof the vigorous next-generation semiconductor memory. Nowadays, the requirement ofFRAM is urgent for China; however, a great number of key technical problems areeager to be solved. Based on the above background，some key research works have beendone in this dissertation aimed at FRAM. The main contents are as following:1．The integrated process of FRAM is studied and successfully accomplished. Thelead zirconate titanate （PZT） thin films are deposited by the radio frequency magnetronsputtering. The effects of the sputtering power, the annealing method and the annealingtemperature on the PZT film’s performance are studied, including remnant polarization,leak current, crystal phase and so on. The optimized sputtering power and annealingmethod are obtained. The etch technology of PZT film, etching damage andcorresponding recovery methods are investigated by several experiments. The volatilityof lead from the PZT thin film at different temperature has been investigated, and theeffects of ferroelectric capacitors process on the CMOS devices and circuits have beenanalyzed. The hydrogen-induced damage to the PZT film and defendable ways areresearched. Other problems in the integration process, such as the hilloch formation andcrack of the PZT，are analyzed and solved. Based on the optimized fabrication process,ferroelectric device testchips have been realized.2．Research and testing of FRAM capacitor model and cell signal. The ferroelectriccapacitor model of HSIM is amended by extracting model parameter from the hysteresisloops fabricated by UESTC. Based on the model, the ferroelectric2T-2C memory cell isdesigned and simulated. The affect of the total parasitic capacitance of the bit-line onsensing margin is analyzed. The integrated of ferroelectric process with CMOS processis accomplished and the chips of ferroelectric memory cell are tested. The maximalsensing margin about1.3V is obtained by adjusting parasitic capacitance of the bit-line. The results approves that the read and write operation of this circuit are correct and thesimulated model is accurate. Based on this model,1Kbit FRAM is desiged andoptimized. The FRAM prototypes are tested.3．A field effect transistor with gate stack of Pt/Pb(Zr_0.52,Ti_0.48)O₃/Pt/Ti/Poly-Si/SiO₂/Si is fabricated and tested. I-V and C-V memory window about1.5V are obtainedat a sweep voltage of±5V and an on/off source-drain current ratio of>104is achieved.The relation between the memory windows and the area ratio of SiO2capacitor and PZTcapacitor （SOX/SF） is researched.4．A novel application of PZT film in high voltage LDMOS device is proposed.The results show that the PZT LDMOS not only achieved triple breakdown voltagecompared with conventional LDMOS with SiO2dielectric, but also has a memorycharacterization. A drain current-gate voltage （Id-Vg） memory window of about2.2Vwas obtained at the sweep voltages of±10V for the350V LDMOS. The retention timeof about270s was recorded for the LDMOS through a controlled Id-Vg measurement.5．The radiation effects and hardening techniques of FRAM are researched. Atotal-dose hardened NPN bipolar transistor is proposed and fabricated. Theexperimental results indicate that after the radiation total dose of100krad（Si）,the currentgain of the hardened NPN is greater10%²0%than the common NPN.6．The mechanisms of single-event upset in FRAM are analyzed by simulation anda novel single event radiation tolerant CMOS device structure is proposed. The singleevent transient voltage pulses height and width are reduced by introducing partial buriedoxide layer and extra doping layers in sensitive nodes. The structure can availablydecrease SEU sensitivity and alleviate the self-heating. In addition, a new nonvolatileDual Interlocked Cell （NV-DICE） storage element is proposed. The cell includes aDICE latch and four backup ferroelectric capacitors. It can perform store automaticallywhen the power is off abruptly and has high tolerance to SEU. The developed NV-DICEcan be applied to nonvolatile memory device which require high tolerance to SEU.