Research On Key Technologies Of High-speed And Low-power Wireline Serial Receiver Supporting Multiple Standards

The rise of new technologies and applications,such as edge computing,auto-driving,high-definition video streaming and industrial Internet of Things,has accelerated the development of high-speed serial interfaces.Data rate of per lane doubles every three to four years.However,with the increase of data rate,the power consumption,signal integrity and circuit complexity of the Ser Des become more severe,these problems cannot be completely solved by improving the performance of CMOS transistors.This is why high-speed and low-power receivers have always been a research hotspot.What's more,to provide more flexible interconnection solutions,reduce the design and time cost of customed SOC system and meet different application scenarios,the proposed receiver can also support more electrical interface standards,such as PCIe 4.0,DP 1.4,USB 3.2 Gen2×2,SATA 3.2 and JESD204B.However,the multi-standard receiver will face more technical challenges.For example,data-related jitter caused by AC coupled channels,different data rates,different channel compensation requirements,higher jitter corner frequency,higher jitter tolerance and even some protocols require that the receiver must support Spread Spectrum Clock(SSC).To solve the above problems and challenges,the research of equalizer compensation and clock and data recovery technology is studied in this paper.Based on SMIC 40nm process,a high-speed,low-power and multi-standard receiver is fabricated,packaged and tested.Firstly,the current mainstream electrical interface standards are stduied.A PVT-insensitive front-end impedance matching network is designed,and challenges of multi-standard continuous time equalizer(CTLE)are analyzed,a CTLE with high bandwidth,high gain and multi-standard requirements is presented.The CTLE is a two-stage cascade structure,the first stage is mainly used for peak gain compensation,and the second stage is used for medium and low frequency gain enhancement to reduce the long-term residual ISI caused by crosstalk,skin effect,etc.Negative Miller capacitance technology and improved negative capacitance technology are adopted to expand the bandwidth and avoid the increasement of area caused by using inductor.In addition,a set of zero is inserted in the negative feedback path of the second-stage equalizer to further improve the peak gain bandwidth.To increase the bandwidth adjustment range,the tail current and the regeneration capacitor of each stage are adjustable.To increase the adjustment range of DC gain,two differential amplifiers are added to the negative feedback loop to increase the feedback path gain,because a larger loop gain can widen the lower DC gain limit.The post-simulation results show that the maximum boost gain of the CTLE is about 30 d B,and the adjustment range of the DC gain can be from-18.4 d B to 4.9 d B.The peak gain bandwidth can be adjusted from 3.7GHz to 11.4 GHz.When the receiver is used in the interface standard with low data rate(<10 Gbps),the power consumption can be further reduced by closing one or all negative capacitor circuits and adjusting the tail current.Secondly,after fully understanding the requirements of multi-standard for CDR,and due to some standards require multiple receiving channels,the best CDR structure for multi-standard receiver is adopted,namely phase interpolation digital CDR.Because with this CDR structure,the proposed 4-lane receiver can share a PLL,which will save a lot of area and power consumption.The noise of each sub-module is analyzed carefully,and a simplified frequency domain model with noise of the whole CDR is established,which will facilitate the overall performance evaluation.Then the effects of loop gain,latency,working frequency on jitter performance and frequency tracking range are discussed,which lays a foundation for circuit design.To reduce the quantization noise of the phase detector,a majority voter based on a moving average filter is designed.The voter has the features of simple structure,low power consumption and low area.Importantly,it can filter out the redundant output of the phase detector in advance.A high-speed digital filter with partial noise shaping technology(PNS-DLF)is proposed,which reduces the quantization noise produced by output truncation of adder in integration path,without consuming too much area and power.By reducing the bit width of phase accumulator,using carry-ahead adder and full-customed digital layout design,the process potential is fully exploited,so that the working frequency of the digital filter can reach up to 5 GHz,which not only increase the jitter bandwidth,but also further improve the jitter tolerance.Finally,based on SMIC 40 nm process and advanced fan-out package,a 5?20Gbps high-performance multi-standard receiver is realized.After packaging,the measured results show that after the CTLE's compensation,the eye opening of 10 Gbps data is 0.68 UI at channel loss of more than 14 d B.With 5000 ppm SSC modulation of10 Gbps PRBS-31 input data,the measured high frequency(>50MHz)jitter tolerance is still 0.34 UI at 10^-12 BER,and the jitter corner frequency is greater than 10 MHz,which meets the current stringent standard jitter tolerance mask,such as DP 1.4,PCIe 4.0 and USB 3.2 Gen2×2.Compared with conventional digital CDR without PNS-DLF,the high frequency jitter tolerance improved by 0.05 UI using the proposed CDR.Moreover,due to the frequency tracking range of CDR is as high as±31 kppm,the proposed receiver is more suitable for some strict standards which need to support SSC applications.With 1.2 V power supply,20 d B channel loss,and 20 Gbps PRBS-31 input data,the power efficiency of a single-lane receiver is 4.3 m W/Gbps,including the PLL power consumption.The area of whole receiver is 760×670?m²,the area of a single-lane receiver is 0.062 mm².The power consumption of the CTLE is only 13 m W and its area is 0.012 mm².In summary,the proposed high-speed,low-power receiver has good performance and can be applied to multiple electrical interface standards,and it has strong academic significance and engineering value.