Design And Implementation Of High-Speed Transmission Interface Based On FPGA

As the development of high-speed internet, the processing bandwidth and the throughput of network equipments increase steadily, and much more requirements and difficulties are needed in the design of data transmission interface. That will be a challenge for designers no matter parallel or serial method is adopted.Nowadays the Intellectual Property Core based on SPI4.2 Protocol (System Packet Interface Protocol level 4, phase 2) is widely used in high-speed parallel interface design, although it's unnecessary to analyze SPI4.2 Protocol, the IP Core is quite expensive, and not flexible enough for placing and debugging. And Aurora Protocol produced by Xilinx Inc. is used frequently in high-speed serial interface design, the definition of data frame of this protocol is not very reasonable, which could waste resources.A method on how to design a high-speed, high-efficiency, high-flexibility and low-cost interface based on FPGA is presented in this thesis according to the requirements of 10 Gigabits packets monitor system over SONET. In the part of high-speed parallel interface design, SPI4.2 Protocol parser which works in 311MHz clock domain is designed locally, instead of using IP Core, to change the format of packets defined by SPI4.2 Protocol into the format required in the system; and as well, normal method for asynchronous FIFO design is modified according to the working environment. In the part of high-speed serial interface design, firstly Aurora Protocol is improved to define a more reasonable frame format and enhance efficiency of network bandwidth; furthermore, Rocket I/O transceiver produced by Xilinx Inc. is got used to realize the high-speed transmission of serial data; and finally, in order to ensure the correctness of transmission, some protection mechanisms is adopted such as synchronous detection, reliability check, flow control and error control. Then, the simulation and test method are introduced briefly.This method is entirely feasible and has been implemented on FPGA chips successfully.