Design And Implementation Of Data Acquisition And Processing Based On High Speed Serial Interface

The high speed data acquisition system is highly used in the modern field of military, aerospace, machinery etc.. The frequency front-end signal system needs to capture and process is also higher and higher which has put forward higher requirements on the high speed acquisition and transmission system. The traditional AD converter mostly uses parallel bus to transfer collected data. With the increase of sampling frequency, the inter symbol interference problem existing in parallel bus is becoming more and more serious, speed has reached the limit. The Only solution is to increase bit width, which has brought great challenge to PCB Layout, it is difficult to guarantee the signal integrity. Compared with the traditional parallel bus, high speed serial bus has very obvious advantages, including: device pin number is less, the area and layers of PCB board is smaller and less, EMI decreased meanwhile the ability of anti-noise enhances. High speed serial bus replacing the parallel bus has become a trend. On the other hand, modern communication and electronic reconnaissance require receiver with the abilities of wide input bandwidth, high resolution and large dynamic range. This requires the receiver to search and monitor within the whole frequency band. If the device searching speed was not fast enough, it will result in leakage alarm because of omitting or losing signal. Channelized receiver is a high intercepting probability receiver, it divides the receiving broadband signal into multiple narrow band signal to process which can achieve very high precision of frequency measurement and anti-interference ability. This makes it suitable for all kinds of electronic reconnaissance systems.This dissertation designs and implements the data collecting and processing system based on the high speed serial connector after researching the key points of the JESD204 B high speed serial interface, which fitting the trend of interface serial. The system chooses the high-performance FPGA as the main controlling chip, using the inherent GTX interface to interconnect with AD and receive sample data. For fully using the inner recourse of FPGA and reducing the difficulty of subsequent processing, the system channelizes the collecting data and put into DDR3 cache. Finally, the stream is sent to the host computer receiving card serial data by using the TLK2711 universal Gigabit transceiver. Because of the standard JESD204 protocol, the system has good versatility and easily connects to all kinds of signal processing cards and supplies pre-processing data. The main work of the dissertation is as follows:1.Analyzing and researching the key points on the high-speed serial interface, including interface circuit, synchronous clock recovery, line coding mechanism, synchronous character detection.2.Researching GTX high speed transceiver structure, characteristic, method of usage and circuit design points.3.Designing AD sampling circuit, researching each module functions of JESD204 B high speed serial interface and using FPGA to realize the interface protocol. Finishing the reading of the AD sampling data. At the same time channelization processing the sample data of Digital.4.Using Xilinx MIG controller to design a virtual FIFO cache unit based on DDR3 memory.5.Designing the general high speed serial data transmitter based on TLK2711. And transmitting AD sampling data which has been processed to the host computer to analyze through the coaxial cable.6.Finally, testing the noise ratio of AD sampling signal, effective data bits respectively, the correctness of logic function and storage of cache module, the correctness of logic function and the transmission of high-speed transmission module. The test results show that the design of the collection and transmission system based on high speed serial interface in this paper is excellent performance and meets the demand index requirement proposed by system.