Research And Implementation Of High-speed Serial Digital Interface Testing Technology

With the development of semiconductor technology and the continuous improvement of chip integration,the demand for data transmission rate between chips is getting higher and higher.High-speed serial digital interface technology eliminates parallel interface technology in many scenarios and integrates into many complex In large-scale integrated circuits(such as FPGA,DSP and CPU),the demand for test capabilities for their high integration and powerful data transmission capabilities is also increasing.How to improve test capabilities to solve the problem of test time and cost has become the focus of the IC industry focus.Although the mainstream discrete instrument test solutions on the market can test the Serdes interface,the test efficiency and test cost cannot meet the requirements of large-scale mass production.Therefore,the test plan of this subject adopts ATE equipment with high degree of automation and strong versatility to test the embedded Serdes interface.The topic is based on the Advantest V93000 automatic test system to study the test method of serial signal embedded with the Serdes interface chip,solve the problems faced in the realization of the high-speed signal test method,and verify the research results through the actual test of Serdes products.The specific research content of the subject is as follows:(1)Overall scheme design.According to the function and test requirements of the embedded Serdes interface,a suitable test system is adopted and a test plan is drawn up to ensure the smooth progress of subsequent tests.(2)Hardware design.Combining test requirements and equipment conditions,design a good test hardware structure,and use existing test resources to design high-speed test load boards.(3)Research on test methods.The research is based on the realization of the test method of the Advantest V93000 automatic test system,and completes the send/receive function test,jitter test and rise/fall time test of the embedded Serdes interface chip.(4)Choose an FPGA product(XCKU040)as the chip to be tested.The highest transmission rate of the high-speed interface of this chip is 16.375 Gbps.The result of the function and parameter test is obtained after the test,which verifies this scheme.Based on the ATE equipment,this subject designed a set of Serdes interface test schemes,and carried out the hardware design,software test program design,and actual operation verification required for the specific test scheme.Finally,the related parameter test of the Serdes interface is realized,and it also has practical value in the identification test of foreign sample chips.