Research And Implementation Of High-speed And High-precision Acquisition System Based On FPGA

With the development of signal processing technology,data acquisition has been applied to all walks of life,and in aerospace with radar measurement fields,the sampling rate of the acquisition system is up to GSPS.However,due to the manufacturing process and technical level,the sampling rate and resolution of ADC(analog to digital converter)are two mutually restrictive indicators.With the improvement of ADC sampling rate,the transmission speed of sampling data will also increase accordingly.Therefore,the transmission interface based on CML(current mode logic)come into being.In order to meet the requirements of electronic information technology for high sampling rate and high resolution in data acquisition,this paper designs a data acquisition system with FMC interface,2GSPS sampling rate and 12 bit resolution,focuses on CML interface protocol,and through the construction of each module in the high-speed acquisition system and the correction of system error,the alternating acquisition of two ADCs is finally completed,and achieves a data acquisition system with sampling rate of 2GSPS,resolution of 12 bit and maximum input analog bandwidth of 1GHz.The main research contents of this paper are as follows:1)The overall function module design of 2GSPS acquisition system.Through comparison and analysis of transmission interface and logic devices,determine the whole module of the acquisition system,including front-end amplifier circuit and signal drive circuit,and according to the clock requirements of JESD204 B protocol,design the system clock network scheme.2)The research on JESD204 B protocol.The sampling data is transmitted to FPGA through JESD204 B serial interface,and then the FPGA splices the data.In order to obtain the correct sampling data,the paper completes the establishment and channel synchronization of the data link between the ADC and the FPGA,and demaps the data output by the JESD204 B protocol.3)The design of time alternating sampling system based on jesd204 b.In order to improve the sampling rate of the system without reducing the resolution,the "alternating" acquisition of two ADC is achieved through the delay processing of two sampling clocks.At the same time,based on the SYSREF signal under JESD204 B subclass 1,the paper designs and implements the deterministic delay,solves the problem of asynchronous multi-channel transmission.4)The errors analysis and correction of TIADC(Time-Interleaved ADC)sampling system.The scheme of time alternating sampling can improve the sampling rate of the system,but also introduce a variety of mismatching errors.A method based on delay filter and sine fitting is proposed to estimate and correct the error mismatching parameters.Finally,the TIADC sampling system is tested and verified,and the test results of the system sampling clock,sampling rate,performance parameters and error spectrum are given.The test results show that the maximum sampling rate of the sampling system is 2GSPS,the resolution is 12 bit,the stray free dynamic range is >70d B,the maximum input bandwidth is >1GHz,the gain accuracy is <0.1%,and the common mode rejection ratio is >60dB.