Design Of A Dual-channel 10GSPS Sampling Rate High-speed Data Acquisition System

Due to the complexity and variability of the signal itself,such as higher frequencies,wider bandwidths,and difficult test environments,it is becoming more difficult and more demanding to accurately capture and reconstruct signals.This means that the data acquisition system must have a high sampling rate while it has a high resolution.However,the current development of high-speed and high-precision data sampling systems in China are still far from the level which were need.The research of high-rate data acquisition system is very necessary and urgent.In review of the current status of domestic high-speed data acquisition systems,this thesis designs a dual-channel data acquisition system at the rate of 10 GSPS.The main research contents are as follows:1.Clock design for high-speed and high-resolution data acquisition.High-speed high-resolution data acquisition modules and high-speed data receiving modules have strict requirements on clocks.Low-jitter,high-quality clocks can improve the signal-to-noise ratio and improve the accuracy of data acquisition.Therefore,it is necessary to design low-jitter,high-quality clocks.At the same time,the clocks of the high-speed high-resolution data acquisition module and the high-speed data receiving module need to ensure the same source.2.Research on JESD204 B serial transmission protocol.The high-speed and high-resolution data collected is transmitted to the high-speed data receiving module through the JESD204 B serial transmission protocol for data assembling,storage,and back-end processing.Therefore,it is necessary to study the JESD204 B serial transmission protocol between the data sending end and the data receiving end.Establish a mechanism.3.Design of TIADC system based on JESD204 B serial transmission protocol.Due to the limitation of the sampling rate of the single-chip ADC,this article will use two 5GSPS ADCs to form a TIADC system to achieve 10 GSPS.At the same time,the JESD204 B serial transmission protocol also requires the establishment of synchronization mechanisms between different sub-ADCs to achieve a deterministic delay in the data acquisition stream.4.Error estimation and calibration algorithm design in TIADC system.Time-sampling sampling system will bring offset error,gain error,and time error.These three errors will reduce the resolution,signal-to-noise ratio and quality of the signal waveform of the sampling system to a certain extent.At the end of the thesis,the core part of the design was tested and verified,and the design index of quantization bits of signal is 12 bits,the analog bandwidth ?3GHz,the dual-channel 10 GSPS sampling rate,and the effective number of bits is greater than 8bits When the analog signal input is 156.25 MHz was achieved.