Design Of A Wideband Acquisition System With 10GSPS Sampling Rate

The data acquisition system is an important part of the electronic measurement equipment,in order to observe these more complex signals accurately,it is necessary to improve the relevant indicators of the data acquisition system,such as sampling rate,resolution and storage depth.At present,the research and development of this high-speed and wide-band data acquisition system is relatively backward in China.Therefore,it is necessary to conduct research on high-performance data acquisition systems.This thesis designs a wide-band data acquisition system with 10 GSPS sampling rate.The main research contents are as follows:1.Wideband acquisition system design.Through the analysis of project indicators and the comparative analysis of design schemes,the design schemes of wideband high-speed data acquisition module,sampling clock module and trigger storage module are given.On this basis,the overall design scheme of wideband acquisition system is given.Among them,the wideband high-speed data acquisition module is a TIADC(Time-interleaved ADC)acquisition system based on the JESD204 B protocol,and the sampling clock module is a sampling clock system circuit that meets the requirements of the project and the JESD204 B protocol.2.The logic design of the receiving sampled data and the realization of the deterministic latency.After analyzing the JESD204 B protocol standard in detail,the logic for correctly receiving and recovering sampled data is designed.The deterministic latency is realized by designing the TX device and the RX device.3.Trigger and memory module design.According to the sampling data rate and the requirements of the data storage depth,the data storage circuit of the DDR3 SDRAM+FPGA architecture that meets the project requirements is designed.Based on this architecture,the data trigger storage logic is designed.Finally,the core circuit of the hardware platform is tested.The test results show that the paper design achieves the expected goal.