Design And Implementation Of JESD204B Protocol On Xilinx Series FPGA

With the development of information technology and the speed of data processing,people's demand for data and the speed of data transmission are constantly increasing,which makes the industry continuously improve the speed of data transmission interface.High-speed data transmission requires high sampling speed and accuracy,which requires high sampling rate and high sampling accuracy converter.Parallel transmission enhances high sampling accuracy,which leads to more pins and more difficult wiring by increasing data bit width;Parallel transmission enhances high sampling rate,and increases the interpin electromagnetic interference and inter-symbol crosstalk by raising the clock;Parallel transmission clock and data synchronization are more difficult.High-speed serial transmission can effectively solve these difficulties.JESD204 B protocol standard is one of the high-speed serial,and there are many high-speed converters integrated with JESD204 B.JESD204B IP core is provided oversea,because of its commercialization,the fee is more expensive.Secondly,the IP core is a "black box" and can not see the internal RTL(Register Transfer Level)structure.For national defense,there are big loopholes.Considering the problems above,implementing JESD204 B IP on FPGA is necessary to do research.The main research work of this paper is as follows:1.Firstly,the core of Gigabit serial technology is explored,and the feasibility of using Xilinx MGT to implement JESD204 B IP is analyzed.Secondly,the synchronous transmission process in JESD204 B standard is studied.The synchronous transmission state transition is designed and realized by analyzing the principle,and the link monitoring module is also analyzed and implemented.2.Verification of JESD204 B IP by Integrated JESD204 B Interface Converter: To validate the JESD204 B IP receiver designed in this paper,it is necessary to use ADC joint test;to validate the JESD204 B IP sender designed in this paper,it is necessary to use DAC joint test.Through logic and inter-board test,logical analysis proves that the JESD204 B IP designed in this paper can establish synchronization,and the upper board test proves that the JESD204 B IP designed in this paper is practical,with a single channel line rate of 10 Gbps.