Design And Implementation Of 12.5GSPS High-speed Data Acquisition Module

The rapid development of science and technology today makes the field of electronic information more and more important for high-precision,distortion-free acquisition,processing and display of various high-frequency signals(especially high-frequency small signals).The accurate collection of various high-frequency signals in the physical world depends on the corresponding high-speed data collection system,and the in-depth study of the high-speed data collection system plays an important role in promoting the development of the electronic information field.This paper is devoted to research in the field of high-speed data acquisition,completing the design and implementation of the high-speed data acquisition module.The key indicators are: the highest real-time sampling rate is 12.5GSPS,the analog input bandwidth is 4GHz,the vertical resolution is 8bit,and the effective number of bits is 6.2bit@500MHz.This paper studies the time-sampling sampling system based on JESD204 B high-speed serial protocol transmission,completes the design of the 12.5GSPS data acquisition system,completes the schematic diagram and PCB design of each system module,and performs system debugging and verification of the acquisition system.The main work completed in this article is as follows:1.Data collection and high-speed transmission technology is researched.According to the project requirements,the key components of the system are compared and selected,and on this basis,the overall plan of the 12.5GSPS high-speed data acquisition system is designed.2.Each key module of 12.5GSPS data acquisition system is designed,including signal drive,ADC acquisition circuit,clock generation and distribution,signal transmission and buffering,digital signal processing and other modules.The problem of signal driving and impedance matching in the TIADC system is analyzed,and the consistency design between different signal channels is combined with the ADC to complete the module design of the signal driving circuit.The ADC analog input circuit design,ADC power supply system design and ADC internal configuration design are elaborated in detail,and the module design of the TIADC system acquisition array circuit is completed.Analyze clock jitter and clock phase-locking principles,elaboratesystem clock requirements,and complete the design of high-precision clock circuit modules.Analyze the working principle of high-speed serial transmission protocol JESD204 B,explain the synchronization process,mapping and demapping process of protocol transmission between ADC and FPGA,and complete the design of high-speed data transmission module.3.Complete the design of high-speed data cache and processing module.Analyze the cache requirements of the system,and design the decelerated cache for the de-mapped ADC data to complete the reconstruction of the data waveform.Study the system acquisition mode,design standard mode,average mode,peak detection and other acquisition modes,and complete the design of the system trigger mode.Through the debugging and testing of the data acquisition system,the key indicators such as the highest sampling rate,analog input bandwidth,and effective number of bits of the 12.5GSPS high-speed data acquisition system designed in this paper have met the design requirements and completed the design goals.