Digital System Design Of 12.8GSPS Acquisition Module

With the rapid development of science and technology,the application of high-frequency circuits has become more and more extensive,and the demand for high-frequency electrical signal measurement has gradually increased.The measurement and analysis of high-frequency signals usually require a high sampling rate,high bandwidth oscilloscope,and requires the oscilloscope to have a variety of data processing functions.Due to the extensive application of computer technology,the demand for plug-in oscilloscopes combined with computer resources has gradually increased.This research is based on the design of PXIe oscilloscope acquisition board,investigates the high-speed data acquisition system based on the JESD204 B protocol and completes the design of the 12.8GSPS data acquisition system.The specific research contents of this topic are as follows:1.A total design of the digital system of the high-speed acquisition module.Combined with the actual needs of the project,a comparative analysis of analog-to-digital converter and programmable logic device is proposed according to the architecture and principles of the high-speed acquisition system.Meanwhile,the appropriate device is selected to construct the acquisition system.Then the clock requirements of the high-speed acquisition system and the impact of clock jitter on the high-speed acquisition system are analyzed.A specific scheme of the clock is also designed in this section.The total design is given based on the above analysis.2.High-speed data receiving and processing design.Analyzed the JESD204 B serial transmission protocol,designed a time-alternating sampling system based on the JESD204 B protocol,analyzed various errors caused by the TIADC system,and designed an error calibration scheme.To receive high-speed sampling data,design an asynchronous FIFO to receive the data synchronously,and then study the relationship between data mapping and de-mapping between ADC and FPGA,and design a high-speed data receiving scheme.At the same time,the synchronization problem between multiple ADCs is also analyzed.In addition,this subject further studies the different acquisition modes of digital oscilloscopes,analyzes the implementation schemes of data processing such as hardware frequency division and peak detection,and gives specific logic circuits.3.Design storage trigger and control block.Firstly,the importance of the trigger function of the digital oscilloscope and the realization principle are introduced,as well as the shortcomings of the analog edge trigger.Then the digital edge trigger scheme is proposed.By analyzing the data throughput of the high-speed data stream of the high-speed acquisition system,a storage circuit based on the external storage device DDR3 SDRAM is designed.According to the timing requirements of the MIG core in FPGA,the logic circuit of DDR SDRAM is designed to realize the read and write control of DDR3 SDRAM.Combining the digital edge trigger and storage control circuit,a method is described to identify the trigger point in a piece of sampled data precisely.The high-speed data acquisition system designing in this work has the highest real-time sampling rate of 12.8GSPS,the vertical resolution of 8bit,and the maximum storage capacity of 2Gpts.It has some other functions such as hardware frequency division,peak detection and large-capacity data storage.It can also find an accurate trigger point through digital edge triggering,so that the waveform can be displayed stably.