Design And Implementation Of Protocol Controller For JESD204B Transmitter

With the resolution and sampling rate of data converter(ADC or DAC)continues to improve,traditional parallel interfaces have become bottlenecks in high-speed connectivity between data converters and programmable logic devices(or ASIC),and high-speed serial transmission between data converters and FPGA has become the industry's main research direction.Among them,JEDEC international organizations proposed a JESD204 B high-speed serial interface,the highest serial channel rate of up to 12.5Gpbs,support multi-device and multi-channel synchronization and deterministic delay.JESD204 B serial interface has the characteristics of high bandwidth and less pin and has a great advantage in the connection between data converter and FPGA.Thereforce,This paper studies the protocol controller of JESD204 B transmitter.Based on the deep analysis and research of JESD204 B standard,this paper designs a JESD204 B transmitter protocol controller according to the requirements of the project,and completes the digital back-end design with TSMC 55 nm 1P7M standard CMOS process.The controller uses quad_byte parallel 32-bit design method and support two dual-channel 14-bit 250 MSPS ADC connection,support subclass0 and subclass1,support deterministic delay and multi-channel synchronization,the controller operating frequency up to 350 Mhz above.At the same time the controller integrated SPI interface,you can easily configure the controller and read the working status information from controllel.This paper first introduces the application field,development history and existing advantages of JESD204 B serdes,and then analyzes the protocol contents of JESD204 B protocol,especially the transmitter part,including transmission layer protocol analysis,scrambling protocol analysis,data link layer protocol Analysis,but also specifically analyzed the JESD204 B new terms——deterministic delay.Then,the module design and simulation of the whole transmitter protocol controller are completed according to the protocol requirements and project requirements.The framer supports two dual-channel 14-bit 250 MSPS ADC data mappings and CS control bits input,scrambler and 8B10 B encoder using a parallel 32-bit design approach,the testability design uses a parallel 32-bit PRBS implementation.At the same time,the JESD204 B transmitter protocol controller designed in this paper is jointly simulated with Xilinx's JESD204 B receiver protocol controller IP core,and the board-level verification of the entire transmitter protocol controller is completed based on the Xilinx KC705 development board.And board-level verification results show that the JESD204 B transmitter protocol controller designed in this paper can communicate with Xilinx's own JESD204 B IP core in line with the design requirements of the transmitter.Finally,based on TSMC 55 nm 1P7M standard CMOS process technology to complete the entire JESD204 B transmitter protocol controller logic synthesis and automatic placement and routing design.