Design Of Dual-channel 6.4GSPS High-speed Data Acquisition Module

As the improvement of signal bandwidth in modern electronic equipments,such as wireless communications,radars,and electronic warfare receivers etc.,the higher performance requirements to data acquisition systems have continuously asked,espectially the high real-time sampling rate,mass storage for samples and data transmission capabilities.Based on a project developed,this thesis designs a high-speed broadband data acquisition module,which possesses dual input channel in sampling rate of 6.4GSPS used in the AXIe chassis.The main research contents are as follows:First,two acquisition schemes which can achieve 6.4GSPS high-speed data acquisition are given and compared.From the perspective of board-level design,resource utilization and system cost,the ADC chip with JESD204 B high-speed transmission interface is finally selected to meet the requirements of data transmission.In order to meet the dynamic singnal input,the front-end conditioning channel design is given in multi-input range.According to the clock requirement of JESD204 B subclass 1,the clock scheme and clock chip selection are given.In order to meet the requirements of on-board trigger storage,a trigger storage scheme is proposed.Based on the above scheme,the overall design and FPGA logic platform selection are given.Secondly,the JESD204 B protocol and its interface structure are introduced,and the three stages of link synchronization establishment process are given.In order to realize the two-channel synchronization based on JESD204 B subclass 1 deterministic delay,the principle of deterministic delay is given,and the optimal design of SYSREF at the transmitting-end,the calculation of the delay value of SYSREF at the receiving-end and the design of buffer delay are shown.The clock circuit and logic design of acquisition and data receiving are completed.The clock circuit includes working mode setting,clock signal generation--clock division and delay.Acquisition and data receiving mainly include channel gain control,ADC function control,JESD204 B IP core control,data buffer and demapping module.Then,the modular design and data transmission design of trigger memory are completed.The logic design of DDR3 read-write is completed and the continuous storage of sampling data is realized through data bit width conversion.The design of trigger storage control module,including storage state machine,trigger storage and segmented storage design is given.The storage state machine is used to realize the selection of storage working mode and storage depth.In the case of continuous multi-segment storage,the ability to capture target signal and the utilization of large-capacity memory can be improved.The trigger storage data is transmitted to the host computer through the high-speed serial transceiver.The design of its upload path is given.Finally,the function debugging and performance verification of the high-speed data acquisition module designed in this thesis are carried out.The correctness of continuous multi-segment trigger storage and high-speed data transmission logic is verfied.The test results show that the performance of the acquisition module meets the standard.The dual-channel data synchronous sampling verification is completed.