The Design Of A High-speed Transmitter Based On PCIe 2.0

With With the rapid development level of consumer electronic devices,the speed and power requirements of such devices are increasing.New hardware devices are demanding higher bandwidth for interface circuits and transmission rates between devices,and the bandwidth of various interface protocols is constantly being updated and upgraded.The Serializer Deseiralizer（SerDes）interface circuitry is not only faster,but low power consumption is also becoming more important.In the consumer market,for faster speed and lower power consumption,most of the interface circuits with transmission rates above 5Gbps use more advanced process nodes.At the same time,as the transmission rate reaches above Gbps,the transmission line becomes more and more attenuated for the signal and the inter-code interference becomes more obvious,which leads to a huge BER of the signal.In order to make SerDes perform more reliably even at rates above Gbps,the circuit structure of SerDes was changed and new circuits appeared,such as a feed-forward equalizer for the transmitter,a judgment equalizer for the receiver,and a continuous-time equalizer.As a result,SerDes circuitry has once again grown by leaps and bounds.In this paper,a low-power transmitter with a transmission rate of 5Gbps is designed based on TSMC 12nm Fin FET process.The main work of this paper is as follows:1)The structure of the classical SerDes transceiver is introduced,the signal integrity issues affecting the transmitter performance and its performance evaluation methods are analyzed,and the principle and operation of the transmitter base module are elaborated.Based on this,the transmitter structure of this paper is proposed.2)A composite parallel-serial conversion structure combining serial and tree-type parallel-serial conversion is designed to process parallel signals by using two-stage step-by-step parallel-serial conversion to realize the function of converting parallel data with a bit width of 20 bits into two serialized differential data.The maximum transmission rate of serialized differential data is 5Gbps.3)A 3-tap feedforward equalizer with de-emphasis equalization and extremely simple structure is designed,which can achieve a maximum de-emphasis gain of3.57d B and a minimum value of 3.36d B.4)A current mode logic（CML）driver with low supply voltage and high swing is designed.This driver adopts a special CML structure,which saves 54%of power consumption compared to the conventional CML structure with the same high swing.5)Based on the transmission line theory,a distributed model applicable to the transmission line of SerDes transceiver is built,and a packaging model is built.In addition,a pseudo-random sequence Pseudo Random Binary Sequence（PRBS20）generation and detection circuit for SerDes transmitter testing is designed.Based on the transmission line model and the packaging model as well as the PRBS20generation and detection circuit,the simulation circuit of this transmitter is built and the pre-simulation function is verified6)The optimal layout wiring structure of the overall transmitter is analyzed,the full custom design of the transmitter circuit layout is completed,and the post-simulation of the transmitter is completed.The simulation results show that the maximum transmitting speed of the transmitter is 5Gbps,the maximum value of de-emphasis gain is 3.57d B and the minimum value is 3.36d B.,the maximum jitter is0.085UI,the BER satisfies 10^-12,and the maximum power consumption is 21.7m W.The performance of the 5Gbps transmitter designed in this thesis complies with the PCIe2.0 protocol specification.