| Today’s wireless communication system, optical fiber communication system, the backplane transmission system, and other communication systems provide high-quality and convenient information service, which greatly promotes the development of people’s life and society. With the rapid development of communication technologies, due to the channel attenuation, crosstalk, reflection, and other non-ideal factors, distortions for the high-speed signals in the transmission process will be increasingly serious. Equalization is a technique to deal with the inter symbol interference (ISI) by compensating the channel transmission characteristics, aiming at improving the signal integrity and reducing the bit error rate. However, with the increase of the signal rate, the design and implementation of high speed equalizer, especially the adaptive high speed equalizer, are facing severe challenges, which need to be optimized and have a good compromise in such circuit parameters as operating speed, compensation capability, adaptively, area and power consumption, to meet the growing demands for communication systems. In this paper, the architectures of the adaptive equalizers used in high-speed serial communication are studied, and on the basis of equalization architecture optimization, and CMOS technologies are used to design a number of high-speed equalizers applied to receivers, and they are taped out and verified.In this paper, the effects of such non-ideal characteristics as loss, crosstalk, reflection and noise on signal transmission are first analyzed in both frequency domain and time domain. According to this together with the existing main stream equalization technologies and their adaptation conditions, the typical back-plane channel is simulated based on the ADS simulation platform. By analyzing and comparing, the factors such as area, power consumption and feasibility are considered, and a combination scheme of optimized linear equalizer (LE) and decision feedback equalizer (DFE) is selected, which is a basis for the research and design of the architecture and the circuit of the following equalizer.According to the structure of the combined equalizer obtained from simulations, a high-speed feed-forward equalizer (FFE)+DFE combined equalizer used in the receiver is designed in this paper. By analyzing and comparing the characteristics of the baud spaced equalizer (BSE) and fractional spaced equalizer (FSE), the FSE architecture is selected to reduce the effects of spectrum aliasing and sampling bias. For the problem that the traditional DFE architecture is difficult to meet the design requirements of high-speed DFE, a half rate architecture is used to improve the signal transmission rate and the accuracy of the clock signal. In addition, during the design of the FFE circuit, the active parallel inductor peaking technology is used to increase the delay line bandwidth. On the basis of this, the FFE+DFE high-speed equalizer is designed and implemented based on TSMC 0.18μm CMOS technology, which is taped out and tested. Test results show that the horizontal opening of equalization output eye diagram is reached 0.84UI at the transmission rate of 6.25Gb/s, which can well compensate the channel with the attenuation of 22dB at 6.25GHz.After the successful design of the high-speed FFE+DFE combined equalizer, a 10Gb/s continuous time linear equalizer (CTLE)+DFE combination equalizer is studied and designed in order to solve the problems that the FFE bandwidth is limited by the process cut-off frequency and the operating speed limitation of the combined equalizer is caused by the high sensitivity of the delay circuit relative to the process bias. By analyzing and comparing the characteristics of passive RLC filter and active differential filter, the CTLE based on active differential filter is designed, and the tuning function is introduced in the circuit, so that the CTLE can effectively compensate the channel. The CTLE+DFE equalizer has been designed and realized based on TSMC 0.18μm CMOS process, and fabricated and tested successfully. The test results show that the horizontal opening of equalization output eye diagram is reached 0.63UI at the transmission rate of 10 Gb/s, which well equalize the channel with the attenuation of 31 dB at 10GHz.Based on the fully research of the combined equalizer architecture, circuit and the way of its adaptive implementation, a 20+Gb/s adaptive CTLE+DFE equalizer was designed and realized with IBM 0.13μm BiCMOS process in this paper. The adaptive structure based on slope comparison is applied to the CTLE which is optimized to reduce the area and power consumption. The analog least mean square (LMS) algorithm circuit is used for updating the tap coefficients of the DFE to achieve a good compromise between speed and performance. At the same time, in order to meet the timing requirements of 20Gb/s and above signal rate, half rate speculative architecture is used in the main structure of the DFE to reduce the delay time of the feedback path. In the end of this paper, we give the chip photos and test results for the proposed adaptive equalizer whose area including pads is 0.78×0.8mm2. Test results show that the eye diagram at the end of channel has closed completely without the proposed equalizer while the 20GB/s data passed over a backplane channel with the attenuation of 20dB and the reflection of 13dB at 20GHz, and the horizontal opening of the output eye diagram is reached 0.85UI with the equalizer. The equalizer work well at the rate of up to 24Gb/s, and the corresponding opening of the output diagram is 0.81UI. The power consumption is 624mW with the power supply voltage of 3.3V.At present, there is still a certain gap in the design and implementation between domestic and international high speed equalizer. This paper not only can promote the research of related fields, having important academic value, and also has important application values for the design of high speed integrated circuits to our country.
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