Design Of A 10-bit High-speed SAR ADC

With the development of communication systems,such as Ethernet network transceivers,high-speed wireless systems,and optical fiber communication fields,etc.They have all put forward higher requirements on digital signal processing technology.As a bridge connecting analog and digital signals,the performance of the Analog-to-Digital Converter(ADC)will directly affect the performance of the digital signal processing system.In medium and high-speed application systems,analog-to-digital converters with medium resolution and hundreds of megabytes of sampling rate are often required.Successive Approximation Register(SAR)analog-to-digital converters are widely used due to their simple structure,low power consumption,and low cost.A 10 bit 200MS/s high-speed SAR ADC is designed for the application of high-speed communication system.Asynchronous timing is used in the whole structure,and asynchronous self clock logic based on comparator is designed to further compress the time and improve the overall speed.In the gate voltage bootstrap switching circuit,the substrate of the sampling transistor is connected with the bottom plate of the charge storage capacitor to reduce the signal feed through and improve the linearity.In CDAC,a capacitor array with binary-scaled recombination weighting method is used,and one bit redundancy is implemented.A suitable redundancy range is designed,so as to relax the requirements of the establishment accuracy.The switching algorithm adopts monotonic switching based on split capacitor,which ensures that the common mode level of the comparator input remains unchanged during the voltage establishment process.The comparator adopts a two-stage dynamic structure,which reduces the power consumption.Aiming at the phenomenon that the comparator may appear metastable when it works at high speed,a new metastable suppression circuit is designed,which can effectively avoid metastable without increasing the delay.Using parallel successive approximation digital logic structure,the parallel operation of comparator and digital logic is realized.Compared with the traditional serial operation digital logic,the logic delay in bit conversion is eliminated,and the overall speed is obviously improved.Based on TSMC 40 nm CMOS process,the specific circuit is built and the overall layout is drawn.The area of the core layout is 155?m × 195?m.Post-simulation results show that the ADC exhibits a 9.68 bit ENOB at Nyquist input frequency when operating at a sampling rate of 200MS/s under a 1.1V supply.The results show that the signal-to-noise distortion ratio is 60.09 d B,the spurious free dynamic range is 68.95 d Bc,the power consumption is 1.84 m W,and the FOM value is 11.21 f J/conv.-step.The design meets the requirements of design index and can be applied in high-speed communication system.