A 12-bit 350MSps Pipeline ADC Design

Pipeline analog to digital converters(ADCs)are used in a wide range of electronic systems such as high performance digital communication systems,high quality video systems and high speed data acquisition systems.The rapid development of these applications is driving the design of pipeline ADCs towards higher speed,higher resolution,lower power consumption and lower power supply voltage with the CMOS technology scaling.This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain and high-bandwidth operational amplifiers(opamps)to achieve high accuracy.This thesis introduces the principle of pipeline ADC and designs a 350 MSps 12-bit pipeline ADC based on 40 nm CMOS process.This thesis first introduces the basic working principle and components of pipeline ADC,and then analyzes the non-ideal factors affecting pipeline ADC.Lastly,the architecture of the pipeline ADC is determined to be 2+2.5×4+3,and SHA-less architecture and capacitor scaling are used to reduce power consumption.Due to the limitation of process and low supply voltage,it is difficult to design a high-gain and highbandwidth operational amplifier.In this thesis,a two-stage operational amplifier is used to achieve low gain and high bandwidth.In order to solve the inter-stage gain error caused by the low gain of the OPA and the capacitor mismatch,a foreground calibration technique based on capacitor trimming is used to calibrate the inter-stage gain error.The core circuit layout area of the pipeline ADC designed in this thesis is 750?m×250?m,and the overall power consumption is 123 m W.The post-simulation results show that at a sampling rate of 350 MSps,the input signal amplitude peak-to-peak value is 1.4V,and a signal frequency within 175 MHz,the SFDR of the ADC is not less than 73.29 d B and the ENOB is not less than 10.11 bit.