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Design And Implementation Of Digital Calibration Method For Pipeline ADC Based On Different Numeric Field

Posted on:2014-06-11Degree:MasterType:Thesis
Country:ChinaCandidate:S QingFull Text:PDF
GTID:2268330401967249Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Due to a good balance between accuracy and speed, pipeline Analog-to-DigitalConverter (ADC) has been widely applied in communication, medical-technology, andbio-technology field. Digital calibration method is a very popular research point insolving contradictory between accuracy and speed, which makes it very valuable.This paper firstly reviews recent researches in digital calibration in both domesticand overseas. Upon summarized advantages and disadvantages of each method, authorpoint out the main research area of this paper.Secondly, briefly introduce ADC structure, analyse error sources, review ADCperformance parameters and theory of Least-Mean-Square algorithm.According to four new problems in conventional error modeling, propose a newimproved Blind-LMS algorithm based on random error model. Simulation results showthat the proposed algorithm has4~10dB improvements in each performance parametersto the conventional one. Meanwhile, the proposed algorithm is faster than and robustthan the conventional one.Considering line noise in sub-micron and nanometer level design, physical designbecomes more and more difficult, especially in mix-signal design, this paper proposesBLMS calibration design in stochastic numeric domain. This paper proposes a newhigh-accurate add-element and a low-complexity and high-throughput multiply-and-addelement. Simulation results show that calibration in stochastic gets a good performanceand can calibration non-linear error in some extent.Finally, find a trade-off between design target and actual design difficulty,implement the first proposed algorithm. Accomplished prototype verification based onMATLAB-FPGA and ASIC design based on SMIC0.13um technology (2*1.2mm2).Simulation under analog circuit results (200MHz sample rate,76.28MHz sine waveinput signal) shows that the proposed algorithm improve SINAD from6.15to76.33,SFDR from36.85to85.78,ENOB from5.71to12.39. Results meet the requirement.
Keywords/Search Tags:pipeline ADC, digital calibration, blind-LMS, stochastic, FPGA, ASIC
PDF Full Text Request
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