The Research And Implement Calibration In14Bit250MSPS Pipeline ADC

As the link between analog world and digital system, the design of ADC is very imortant to the all the system. When ADC work for the domain like software radio and digital image processing, it needs higher speed and more accuracy. The Pipeline ADC has more advantages in speed, accuracy, power consumption and area than the other types of ADC. Recently,the design of pipeline ADC receives a widely attention. But pipeline ADC contains all kinds of non-ideal effects.Without calibration,it is very difficult to improves the precisions above12-bits.This paper presents a scheme of foreground digital calibration for a14-bit250-MS/s pipeline ADC. The proposed digital calibration corrects the linearity errors resulted from capacitor mismatches, finite Operational Transconductance Amplifier gain and comparator settling error in digital domain.This calibration algrorithm is based on the fact that concalculates the height of jump-point in the transmission curve to get theerrors and uses add-on digital logic to subtract errors digitally from uncalibrated digital outputs.The errors are directly measured during the calibration and stored in memory. This errors are later addressed and recalled using the digital output from the first and second MDAC.The digital logic only contains adder and shiter and is easy to be implied.Simuliation results based on Matlab&Simulik behavior mode of a14-bit250-MS/s pipeline ADC shows the calibration technology is useful.And this paper also presents how to establish the RTL circuit and get the layout with the floorplan tools–SOC Encounter9.1.The prototype ADC fabricated in a0.18um CMOS process occupies an active die area of0.52.5mm2.After calibration, the precision of ADC are improve from12.1bit to13.28bit, the Spurious Free Dynamic Range and Total Harmonic Distortion of the ADC are improve from72.5dB to95.2dB and from-64.2dB to-75.5dB, respectively.