Design Of Adaptive Frequency Scaling System Based On Voltage Droop Detection

Supply voltage guard-band(V_GB)is usually added to the minimum operating voltage in digital chip design,that is,a certain voltage margin is left to ensure that the chip can still work properly in the worst case.However,in actual work,the worst-case scenario rarely occurs,and the V_GB thereby brings additional power consumption.In terms of this problem,an effective solution is to use the adaptive clocking method to reduce the impact of on-die supply voltage droop by directly adjusting clock frequency when voltage droop occurred.Therefore,the V_GB can be effectively reduced and the energy efficiency can be improved.Based on the above strategy,an adaptive frequency scaling system for voltage droop detection is proposed in this thesis.The system can sense the voltage variations by monitoring the path's timing,and immediately adjust the clock frequency according to the voltage warning signal.The main work and innovations of this thesis are listed as follows:1)A voltage droop monitoring design consisting of a configurable monitoring path and delay line sampling is proposed,which solves the problems such as limited operating frequency range and large quantization error in the oscillation loop monitoring design.In this design,NAND gate is adopted as the delay unit,which lessens the delay line stages to simplify the circuit structure and reduce the circuit area.2)The delay locked loop is used to generate clocks of different phases,and a single-cycle fast frequency scaling circuit is realized by constantly switching between these clocks.The circuit can work stably from 700 MHz to 2 GHz and has strong anti-interference capability.The delay locked loop will not lose lock until the voltage fluctuation exceeds 80 m V/10 ns.3)A glitch-free clock switching method is proposed to solve the possible glitches when switching between the scaled clock and the original clock.Based on the SMIC 28 nm process,the area of droop detector is designed as 45×44?m² while the area of the frequency scaling circuit is designed as 100×150?m².Simulation results show that the quantization code of the droop detector has a good linearity with the voltage change,and the voltage sensitivity is about 5 m V/1 bit.The voltage droop of different amplitudes can be effectively detected by configuring the threshold of the droop detector but showing no response to those frequently-appearred small voltage fluctuations.The frequency scaling circuit can respond to the voltage warning signal within a cycle with a 9.1%?16.6%system performance loss,and and the jitter of the scaled clock is only 4.2%of the clock period.