Research And Application Of Adptive Clock Synchronization Technology Over Packet Transport Network

With the rapid development of network technology, the tranditional TDM network basing on circuit-switched towards Packet Transport Network(PTN) and realizing the combination of traditional communication networks and widely used PTN have become a important part of the construction of multi-service convergence network. But during the process of realizing the combination of the traditional communications networks and PTN, there will be a lot of problems, such as how to protect the QoS of TDM services over PTN, data encapsulation type, and clock information distribution and so on. While transmitting synchronization services with real-time requirement in packet networks, how to ensure clock synchronization of PTN is the most important problem to be solved firstly.The PTN basing on packet-switched was originally established for the transmission of asynchronous data which was transmitted asynchronously between nodes, and the PTN network does not require strict clock synchronization. If considering transmitting the traditional TDM services over the PTN, we must consider the distribution of synchronization timing information over the PTN. Timing information distribution over the PTN can use the external clock synchronization, Synchronous Ethernet Technology or packet-based Adaptive Clock Recovery(ACR). External clock synchronization and Synchronous Ethernet Technology need the related hardware support, which increases the cost of network construction. The ACR can use the software program to achieve synchronous clock recovery and clock synchronization, which reduces the cost of network construction mostly, but this technology is affected by Packet Delay Variety(PDV) of PTN, designing good filtering algorithm is the key to realize the clock synchronization.After researching on the ACR to realize the clock synchronization of PTN, and then on a FPGA of a sixteen channels-El accessing board,which supports the packets transport, using an ACR method based on the packets to realize the2M clock recovery of TDM service over PTN. By extracting the timestamp information in the packets to control the local clock recovery, even extracting the least delay of packet delay during one minimum to be filtered to eliminate the effect of PDV and loss of packets on clock recovery. The main task of this clock synchronization scheme is to design a timestamp processing unit, which realizes the function of Digital Signal Processor(DSP) function to process the timestamp information. In this design we don’t use the special DSP chip, but in a FPGA chip by customizing the Nios II core to output Frequency Control Word (FCW) to control the output frequency of Direct Digital Synthesizer (DDS), and the Nios II core realizes the function of DSP. To control a pulse overflow DDS to recovery2M traffic clock of TDM service, but we don’t use the special DDS chip, instead of designing a phase accumulator and get the2M clock output though the Most Significant Bit (MSB) of phase accumulator. In order to speed up the recovery clock locking to the transmitter’clock, design clock fast lock and slow lock to dynamically control the recovery of local clock. During fast lock process the least squares method is used to output Frequency Control Word(FCW) to control the output frequency of DDS; During the process of slow lock the76order FIR filter is used to output FCW.In order to chek the feasibility of this design we carryed out some tests, the test results show that the recovery clock performance meets2M traffic interface standard of±50ppm frequency offset specified in ITU-T G.823and other realated standard needs, and This clock synchronization scheme successfully achieves clock synchronization of TDM services over PTN.