Research And Implementation Of Low Power Design Based On Clock Network

With the development of process in integrated circuits design, the exponential increase in chip density lead to power increase which has a negative effect on chip quality. How to reduce the power has become a key factor for a designer. This paper studies low power design methods from three aspects of clock network power based on the analysis of power sources,First of all, this paper discusses one kind of clock division low power design method which considers the reduction of clock frequency. Rely on different clock phase relationship, the data path can reach a high performance between low frequency clocks. Using this method in paths which need a high clock frequency control while other paths stay in a low state can reduce the power of the design. The effect of the power reduction depends on the proportion of paths using this method. By the comparison of using this method or not in ASIC DX project, the experiments show that this method can reduce the power significantly indeed.Then focusing on reduction of capacitance load, clock tree construction cell choosing and clock network structure topology optimization are two strategies analyzed in this paper to optimize the chip power. By the mixing use of construction cell and reduction of clock tree scale, the experiment shows a good result.At last, considered the factor of clock activity this paper explains the clock gating low power technique and how to use it to achieve clock division. With two implementation strategies of using clock gating or not in X-DSP project, the experiments show that by using clock gating and using clock gating to achieve clock division can reduce dynamic power significantly, mean while be good for clock tree balance.