Design Of A 7-bit High Speed SAR ADC

The communication system has been keeping the demand for the medium to low precision high speed analog to digital converters(ADCs)to transmit electrical signals or optical signals.Among the commonly used ADCs,successive approximation Register(SAR)ADC has become a research hotspot because of its simple structure,high digitization and no complex analog circuit.Moreover,with the process scaling,the power consumption of SAR ADC is gradually reduced,the speed is faster,and the performance is more competitive.In this thesis,a 7bit high speed SAR ADC is designed based on the ADC architecture of 1-Then-2bit/cycle.In order to achieve high speed design requirements,a circuit based on synchronous clock is designed,and a simple logic circuit based on delay is improved to increase the duty cycle of comparison clock.After the five frequency division circuit divides the input high frequency clock,the sampling clock and conversion clock are generated by the non-overlapping clock generation circuit,and then the comparison clock is generated by the wide duty cycle comparison clock generation circuit.In the conversion process,SAR ADC first performs 1bit/cycle conversion,and then performs 3 times of 2bit/cycle conversion to complete 7bit quantization.In order to reduce the influence of the offset of the comparator,this thesis proposes a charge sharing offset calibration scheme,which reduces the absolute offset of the comparator through the foreground calibration module,and then reduces the relative offset of the comparator through the background calibration module,so as to ensure the dynamic range and linearity of the SAR ADC.SAR logic circuit and latch window circuit based on negative pulse triggered semi dynamic flip-flop are designed to ensure the high speed operation of SAR logic.Based on TSMC 40 nm CMOS process,the circuit and layout are designed.The post simulation results show that under 1.1V supply voltage,when the sampling rate is 500MS/s,the ENOB at Nyquist frequency input can reach6.69 bit,the SFDR is 51.29 d Bc,the power consumption is 4.12 m W,and the Fo M is 79.81 f J/conv-step.The simulation results meet the design requirements.