Design Of A High-speed Self-calibration CMOS Clock On Chip

With the high development of the digital signal processing and the telecommunica-tion technologies, AD/DA conventers are required rapid development to follow the stepsof theirs as the interface between analog and digital signals. Recently, ADCs tend tohave higher speed and higher precision, and the clock module is definitely the key toguarantee the whole performance. It is more and more important for the design of highspeed clock on chip.Nowadays, the clock generator based on PLL is such a proposal that can provide avariety of frequencies with lower cost and more efficiency. After the summarization ofinternational and national research dynamic state on phase-locked loops and the anlysisabout PLL theories, a new clock design used in high-speed ADCs is putforward-design of high-speed self-calibration CMOS clock on chip. Self-calibrationis that the output clock is feed back to the input of duty cycle stabilizer (DCS) circuit.Comparing with other clock generator designs, in this design, the input signal is used ascontrol signal instead of reference clock signal with edge-triggered mode. The wholearticle shows the design circuits of every module and anlysis about them.The whole stuff is simulated under Cadence Spectre based on SMIC0.35μmCMOS process. For the input signal at100M, duty cycle ranged from10%to90%canmeet the requirement of the50%±5%regulation band. The locking time of the loop isless than500ns and the peak-to-peak jitter is less than13.5ps. This circuit can be totallyapplied for high-speed ADCs.