Design Of A 1-MS/s 12-BIT Low-Voltage SAR ADC

With the rapid development of integrated circuit technology and wireless communication technology,there has been a growing interest in the implantable,portable,and wearable applications.Analog-to-digital convertor(ADC)is the important interface between the natural analog signal and the digital signal that can be processed,which plays an important role in wireless communication.In order to satisfy the requirement of wireless sensor network that are highly-integrated,low-power and long-life,it has been a research focus on low-voltage and low-power analog-to-digital convertors.A 12-bit low-voltage SAR ADC is proposed in this thesis.Firstly,the basic principle and some important performance index of SAR ADC are expounded.Furthermore,some common low-voltage design techniques are also discussed.Secondly,in this thesis,the capacitor switching schemes are investigated,whose advantages and disadvantages are analyzed.Moreover,a binary capacitor array and low-power capacitor switching scheme with two reference levels for low-voltage SAR ADC are presented,which reduce the number of capacitors and the common-mode voltage variation of the digital-to-analog convertor(DAC).Thirdly,a split capacitor array is proposed,where all capacitors are split into two equal capacitors,except for the LSB capacitors and dummy capacitors.In addition,the merge-and-split capacitor switching method and floating switching method are used in the proposed switching scheme.The capacitance of the unit capacitor is optimized by the requirements of matching and thermal noise of switches.Moreover,sampling switches are optimized for better linearity and sampling errors.A low-voltage comparator with offset cancellation is designed,which is composed of two stages of pre-amplifiers and a latch.Additionally,the pre-amplifiers are optimized according to lower power dissipation and better noise performance.Finally,synchronous sequential control logic is used in the proposed SAR ADC.The circuits of the proposed SAR ADC are implemented TSMC 130nm CMOS process.After physical layou:t design which occupies 500?m×390?m,the post-simulation results show the SNDR of the proposed ADC is 67.1 dB,thus the ENOB is 10.9 bit with overall power consumption is only 10?W,while the analog and digital power is 0.6V and sample rate is 1MS/s.Consequently,the results satisfy the design requirements.