Reserch And Design Of High-speed Low-Power CPPLL Fabricated In 65nm

As a core part of SerDes,phase-locked loop?PLL?provides accurate clock guarantee for receiver,transmitter and clock recovery module.High-frequency,low power and low jitter phase locked loop is one of the hotspots.In this paper,the characteristics of charge pump phase-locked loop noise and phase-locked loop noise model are analyzed in detail.The non-ideal factors of the circuit are optimized in the design process,the phase-dead zone is eliminated,the current mismatch of charge pump is reduced,the output clock jitter is minimized,D/A converter is implemented.The design uses 65nm CMOS technology,as a clock generation circuit applied for 5Gbps SerDes design.Reference clock 125MHz,at 10^-12BER conditions,the random jitter is 3.13ps,the deterministic jitter is 4.6ps and the total phase jitter is less than 0.2UI by Matlab noise modeling simulation.In the case of different PVT can be properly locked,and the locking time is less than 1us.This artical builds on that information,for the demand of 16Gbps SerDes,the working frequency to be 8GHz phase-locked loop is designed.Using pseudo-differential two-stage ring oscillator structure to provide four-phase,the operating frequency of8GHz quadrature clock,the use of C²MOS logic frequency divider circuit and AC coupling buffer greatly reduces the circuit power to the layout area,operating frequency up to billions of Hertz.The low-speed divider uses a semi-custom design process to shorten the design cycle and simplify the complexity of design,saving layout area.Dual operational amplifier compensation charge pump can reduce the current mismatch to0.02%,improving the overall loop stability.Removing the digital-analog signal conversion module,the circuit is added to the oscillator start circuit,shortening the lock time.Reference clock 125MHz,at 10^-12BER conditions,the random jitter is 0.53ps,the deterministic jitter is 2ps and the total phase jitter is less than 0.2UI by Matlab noise modeling simulation.In the case of different PVT can be properly locked,and the locking time is less than 0.5us.Under TT corner,the total power dissipation is 13.7mA form 1.2Vand the area of the chip is 0.01mm².