Design And Implementation Of Scheme To Mitigate Write Disturbance Based On Phase Change Memory

With the continuous development of embedded technology,a variety of Internet of Things(IoT)devices are widely used in marine monitoring,aerospace,fire safety and other scenarios.Due to the constraints of its own size and the space scale of application environment,memory capacity and system power consumption have always been the shortcomings that IoT devices need to overcome.At present,most IoT devices use Dynamic Random-Access Memory(DRAM)as main memory.DRAM is a volatile memory,which loses data when power is lost,and its necessary refresh operation also increases system power consumption.DRAM encounters scaling bottleneck under 20nm technology node,so it is difficult to improve chip integration and make a greater breakthrough in memory density.Therefore,the main memory system based on traditional DRAM cannot meet the requirements of high memory capacity and low power consumption of IoT devices.Phase Change Memory(PCM)is a kind of Non-Volatile Memory(NVM),has the characteristics of no data loss after power loss,low power consumption,high scalability and so on.Compared with traditional DRAM,with low power consumption and high density,PCM is more suitable to be the main memory of IoT devices,which helps to improve performance and save energy consumption.However,with the continuous reduction of the size of memory cells,high-density PCM will encounter Write Disturbance(WD)errors that cannot be ignored in 20nm and below technology nodes.Write Disturbance error means that the value of some memory cells may be changed during write operation,thus destroying data reliability of memory and affecting normal execution of program and devices.While constructing PCM based main memory system,it is necessary to solve Write Disturbance problem that affects data reliability.In order to solve Write Disturbance in PCM,researchers have proposed a series of solutions.Write Disturbance errors are caused by heat dissipation between cells,so a simple solution is to enlarge cell space to increase the effect of thermal insulation,but this scheme seriously reduces memory density.This paper proposes a design scheme to alleviate Write Disturbance in PCM to ensure data reliability of PCM and normal operation of devices.At word line level,compressing and encoding the data to be written,that is,data preprocessing to reduce the data patterns that cause Write Disturbance errors,and then processed data will be written to memory.At bit line level,allocating memory resources reasonably,optimizing the read operation for verifying data,and an error correction library is established to eliminate Write Disturbance errors.When reading out the data from memory,we need to find the corresponding memory block and query the error correction library,and finally decoding and decompressing the data in proper order.In this paper,the proposed scheme is simulated and compared with the existing scheme.The experimental results show that,compared with the basic scheme(verification and error correction),Write Disturbance error rate is reduced by 66.8%,and overall overhead is reduced by 16.5%.After completing verification and evaluation,this paper deploys proposed solution to Field Programmable Gate Array(FPGA),to achieve the design scheme mitigating Write Disturbance.FPGA is a bridge unit during the process of reading and writing of PCM,dealing with the read and write data respectively to ensure the data reliability of PCM and the correctness of data interaction between processor and memory.In this paper,the design scheme of Write Disturbance mitigation based on PCM is proposed and verified,and then deployed on FPGA hardware platform to implement the scheme,which has feasibility and application prospects.