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An Architectural Technique For Memory Controller To Improve Lifetime Of Phase Change Memory

Posted on:2019-08-24Degree:MasterType:Thesis
Country:ChinaCandidate:Y ShiFull Text:PDF
GTID:2428330590992295Subject:Computer technology
Abstract/Summary:PDF Full Text Request
DRAM has laid the foundation for designing main memories for decades.However,it is becoming difficult to scale DRAM down to smaller feature sizes.And the energy consumed by DRAM is large,which accounts for 40% of the total power consumption in computer system.In recent years,plenty of new technologies have been proposed to solve the problems mentioned,among which Phase Change Memory(PCM)is regarded as a promising candidate to substitute DRAM with the features of byte-addressable,high scalability and low power consumption.Unfortunately,compared with DRAM,write latency of PCM is much larger.The undesirable write latency will tremendously increase the effective read latency,which leads to poor system performance.PreSET is proposed to alleviate the problem caused by write latency.In PCM,the latency of a SET operation is almost 8 times that of a RESET operation.A write operation concurrently writes hundreds of bits to the memory system.And it is inevitable that SET operation occurs during the write operation.Hence,write latency is always independent with SET latency.As soon as a cache line is marked as dirty,a PreSET operation in advance SETs all the bits in the related memory line.Later,when the write operation arrives at the memory system,only RESET operations happen.Therefore,PreSET reduces write latency,which results in the significant promotion of system performance.Nonetheless,PreSET is quite expensive when poor endurance of PCM is taken into consideration.PCM cells can endure only limited times of rewrites.And PCM cells fail soon when suffering intensive write.PreSET which produces plenty of extra write operations makes the situation even worse.In fact,the number of dirty words in a dirty line is quite limited in most applications.If we only pro-actively SETs the dirty words.Then,write operation only does RESET operations in those which just have suffered SET operations,we could tremendously extend lifetime of PCM while still achieving desirable system performance.Motivated by the observation,we propose Partial-PreSET on the basis of PreSET.The experiment statistics show that,in contrast with PreSET,Partial-PreSET extends lifetime of PCM up to 2.79 X,while only losing around 2%system performance.
Keywords/Search Tags:Phase Change Memory, Memory architecture, System performance, Write endurance
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