Research Of Write Operation Optimization Strategy Based On PCM

Phase-change memory (PCM) is a resistance-based non-volatile memory which proves to be very scalable, while it is a great challenge to fabricate high density DRAM beyond 22nm。Furthermore, PCM requires no refresh operations due to its non-volatile nature and it consumes almost no static power. But PCM also has its weaknesses, such as poor write performance, high write energy consumption, and limited write endurance. Besides, PCM has asymmetric properties:the one is that its write latency is much longer than read latency; the other is that writing a one to a PCM cell needs longer time but less electrical current than writing a zero. Typically, the time writing a one bit to a PCM cell is 430ns and writing a zero bit is 50ns. And the electrical current to write a zero is between 2 and 3 times of that to write a one.Considering PCM’s asymmetries, Flip-N-Write scheme replaces a write operation with a read-modify-write operation and uses a "flip bit" to limit the maximum number of bits to program. This scheme doubles the bandwidth of a PCM device and improves its write endurance. Two-stage-write scheme divides a write into two stages: in the write-0 stage all zeroes are written at an accelerated speed, and in the write-l stage all ones are written with increased parallelism without violating power constraints.However the two-stage-write scheme may cause unnecessary bit changes. For example, if new data are the same to old data, all one bits in the cells are reset first and then set to one. These unnecessary changes lead to a negative effect on write endurance.In this paper we propose a three-stage-write (3 Stage-Write) scheme to improve PCM’s write bandwidth, write energy consumption, and write endurance under the instantaneous write power constraint.In our scheme, write operation is divided into comparison, write-0 and write-1 stages.Every PCM write unit has a flip-bit which marks whether the data of it are flipped or not.In the comparison stage, new data and old data are compared and their difference is used to determine the flip-bit. If the number of different bits is greater than half of the data width, the flip-bit is set to one and new data are flipped. The re-encoding policy reduces the number of changed bits by half on average. Then the flip-bit and re-encoded data are written to PCM cells in an accelerating manner. All zero-bits and one-bits are written separately in later two stages to avoid the time waste in traditional write. The scheme can take the full advantage of the asymmetric properties of PCM for writing a one and a zero to speed up the write operation.We developed a trace-driven tool and evaluated our proposed scheme. Experimental results showed that 3 Stage-Write reduces on average 43.5% bit changes, 16.6% write time and 34.6% write energy consumption over two-stage-write with inversion.