| Nowadays,with the high-speed development of the Internet of Things and 5G communications,there are endless types of electronic audio equipments.Analog-to-digital converters(ADC),as a key component of various audio equipment,play an important role in realizing the conversion of analog signals to digital signals.Sigma?delta ADC becomes the most popular research object in the high-end audio field due to its high precision and high linearity.The main goal of this article is to design a digital down-sampling filter with high resolution and low sampling rate,and to reduce circuit hardware consumption and chip area through a series of measures to meet the needs of high-end audio equipment.The overall design is divided into two parts: First,build the simulink model and simulate of the sigma?delta modulator;second,complete the MATLAB design and RTL design of the digital downsampling filter,and complete the hardware verification based on the FPGA platform.The main research results and contents of this article are as follows:(1)Use MATLAB to model and simulate the sigma?delta modulator of 4th order 64 times oversampling CIFF structure.It mainly includes the parameter determination,structure selection and simulink modeling of the modulator,etc.The final SNR is 114.d B.At the same time,considering the impact of non-ideal factors to build a non-ideal modulator model and complete the simulation.The final SNR is 99.8d B,which still meets the design requirements of greater than 98 d B;(2)Use MATLAB integrated FDATool toolkit to complete the design and simulation of filters.The digital down-sampling filter mainly uses a three-stage cascade form of CIC cascade filter,compensation filter and half-band filter.The CIC filter uses a 5-stage cascade form with 16 times down-sampling function,and which is placed in the first stage of the overall filter;the middle stage is a compensation filter,and a 15-stage FIR filter is used to achieve the amplitude increase and is used to compensate for the passband roll-off formed by CIC cascaded filter.the half-band filter is the last stage,and the order is 32.Finally,the overall filters achieve a stop-band attenuation of more than 80 d B and a passband ripple of less than 0.02 d B.(3)Design and improve the hardware structure of CIC cascaded filter.In this paper,a 5-level CIC traditional cascaded filter structure is designed,including 5 integrators,5 comb filters and a decimator.Then use the Hogenauer truncation theory to reduce the word length of the internal registers of the filter.Compared with the maximum word length theorem,the filter performance is maintained and reduces the unnecessary resource.(4)Design and improve the traditional FIR structure of compensation filter and half-band filter.First,design a traditional filter structure that meets the time domain and frequency domain functions according to the design requirements,and then use the following methods to improve the traditional structure.First,combine the Nobel identity replacement principle to advance the position of the decimator;second,use the coefficient symmetry of the FIR filter to accumulate branches with the same coefficient and then multiply the coefficient;third,use polynomial decomposition technique to decompose the original input signal path into two branches,odd and even.Finally,compared with traditional filters,the filter designed in this paper achieves 64 times downsampling and filter function,and with smaller hardware and lower power consumption.(5)Complete the RTL design and hardware verification of filters,and propose an improved method for the multiplier.Firstly,according to the bottom-up principle,use the Verilog HDL language to describe the all filters.Subsequently,complete the timing simulation of the filters on the Modelsim platform.Finally,download the compiled program to the FPGA board to complete the board-level verification through signaltap in Quartus ?. |
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