| Sigma-Delta analog-to-digital converter (ADC) is composed of Sigma-Delta Modulator and digital filter. Compared to traditional ADCs, the most important advantage of Sigma-Delta ADCs is that no complicated analog circuit structures are required, making it possible to continue decreasing the cost and to be integrated into other digital chips as well. Therefore, Sigma-Delta ADCs have been widely used in digital signal processing areas.In this thesis, a third-order Sigma-Delta modulator with 20 KHz input bandwidth and 14-bit precision, applicable to VoIP (Voice over IP) chips, was firstly studied. The MASH (Multi-stage Noise Shaping) structure was used to design this third-order 1-1-1 cascade Sigma-Delta modulator. After establishing the modulator model in Matlab, each integrator was simulated, and the coefficients of each module were discussed and adjusted, making sure the integrator output not overload. By Z-transformation of discrete signals, expressions of the Sigma-Delta modulator output at each stage were deducted. The circuit for removing quantization noise was designed, and output signals of all stages were unified. The behavioral-level simulation results indicate a SNR of large than 86 and a precision of 14 can be achieved, meeting the design requirements.Then the post-processing method for Sigma-Delta modulator's output signals were studied. The structure of Sigma-Delta modulator is similar to a dual-slope ADC, including an integrator and a comparator, and a feedback loop of one DAC (Digital-Analog Converter). The built-in DAC acts like a switch by switching the integrator input to a positive or a negative reference voltage. The input analog signal is sampled at a very high frequency and the difference between two samplings is quantified to get digital signal, i.e., Sigma-Delta code. The code is then sent to a digital decimation filter, getting the high-resolution linear pulse code modulated digital signals. The decimation filter is thus similar to a code-converter. Signals sent to Sigma-Delta ADC are quantized at very low resolution (1-bit), but the sampling frequency is very high. After being processed by the digital filter, this the over-sampling rate is reduced to a relatively lower sampling rate, and the resolution of ADC can be raised.In this thesis, a multi-stage down-sampling filter was designed to reduce the high frequency output signals of the modulator. The frequency characteristics of the cascaded integrator comb (CIC) filter was analyzed, with appropriate structure and order determined. The sampling frequency of the input signal decreased 16 times, and the quantization noise at high frequency was attenuated. The half-band filter, as a second-level down-sampling filter, was designed by using Kaiser Windows method and the best uniform approximation method, respectively. Based on detailed comparisons of their simulated performance from filters designed by the abovementioned two methods, the best uniform approximation method was chosen for design. Moreover, after considering the large amplitude attenuation effect of CIC filter on useful signals in the passband frequency, a compensation filter was designed, and 2 times down-sampling was realized. Finally, the system-level simulation of filter was performed, indicating that passband cut-off frequency was 20 KHz, the passband ripple was 0.005dB, the stopband cut-off frequency was 93.4 dB, and the down-sampling rate was 64, all basically meeting the design requirements. |
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