Research And Design Of Continuous-time Sigma-Delta ADC

In communication, radar, detection and other real-time application fields, dataprocessing and data acquisition are developing with a trend of integration. Theirsystems become parameterized and platformized. And their modulating algorithmsneed to be updated based on requirements too. Therefore solid ified, non-transparentprocessing approaches become difficult to adapt to the new emerging needs. It isvery necessary to use discrete components and configure ADC dynamically in study.Continuous-Time Sigma-Delta ADC has a feature of low-cost, high-resolution,high-bandwidth and low requirements for parameter match of analog devices, whichmakes it possible to use discrete components to finish the imp lementation. Thisdesign builds a high-performance continuous-time Sigma-Delta ADC throughhigh-speed analog device and FPGA processing chip, which is low-cost andcompact.Continuous-Time Sigma-Delta ADC is constituted by two parts, Sigma-Deltamodulator and decimation filter. This dissertation is divided into two parts,theoretical design and hardware imple mentation. First, the oversampling and noiseshaping technology will be analyzed in detail, then the Sigma-Delta modulatorprinc iple and common structure will be analyzed deeply, and then a comparativeanalysis will be done on the discrete-time and continuous-time Sigma-Deltamodulator’s advantages and disadvantages on sampling network, clock frequencyand clock jitter, drawing a conclusion that continuous time Sigma-Delta modulatorcan achieve a higher bandwidth. Based on this, the structure of the modulator, thebits of quantizer and oversampling ratio will be determined. The Sigma-Deltamodulator system will be designed with its system model to be built using Matlab.Decimation filter adopts the cascade form of CIC filter, compensation filter andhalf-band filter to reduce resource utilization and improve the operation effic iency.the theoretical design Completed, high-speed analog device and FPGA processingchip will be used to finish Sigma-Delta ADC’s hardware design, each moduleanalyzed and introduced in detail. the transposed form of direct symmetricalstructure will be used to achieve compensation filter and half band filter, and theCSD encoding technology process will be used on the filter coefficient. Thisfurther improves the efficiency of the decimation filter operation. Debugsimulation proves that the system has achieved8bit resolution and meets thedesign requirement. Using the research results of this design, achieve a higherbandwidth ADC system can be achieved through simp le improvement.