Sigma-Delta Modulator Emulational Data Processing

Oversampled sigma-delta ADC based on sigma-delta modulation technology are well-suited to the implementation of analog interfaces in digital communication and signal processing systems. These converters exploiting the enhanced speed and circuit density of modern VLSI technologies, have been widely used for high resolution A/D conversion. Sigma-delta modulators, combined with oversampling, effectively attenuate the in-band quantization noise in the output signal and enhance the SNR through the shaping of the quantization error, make it is possible to do high-resolution converter using coarse converters. The analysis of emolational data modulator playing a guidable pole when designing sigma-delta modulator, can provide reference for choice of parameters and character.The structure and circuits of sigma-delta modulator which applied in audio signal range with 10KHz base band and 12bits resolution have been researched. The principles of sigma-delta modulator have been discussed firstly and the influences of structure and parameters on resolution have been analyzed. Then on the base of theories, the Simulink toolbox of MATLAB has been used to make behavior modeling and simulation, and the program achieved the decimation and reducing noise function of digital decimation filter, spectrum and SNR can be gotton by FFT analysis. In order to make full behavior simulation of sigma-delta modulator, the noise models have been set, taking into account most of the sigma-delta modulator's non-idealities and the final result supports the noise models. Last, the main circuits of modulator have been designed, such as operational amplifier, integrator, comparator and clock generator. These circuits have been simulated and verified in Cadence Spectre. The results were analyzed in MATLAB and compared with the above data of models.It is shown that, the designed structure of the second-order sigma-delta modulator can achieve 74.3dB SNR, 12.05bits ENOB on the conditions of 1.28MHz oversampling clock, 64 oversampling rate. The practical circuit of the modulator has been implemented, all the crucial circuit blocks designed can meet the design requirements. The result of circuits verified the legitimacy of this method.