Research On Key Technology Of 12-Bit 1.25GSps Current-steering DAC Based On Octagon-switch Units

With the rapid development of wireless communication fields,such as broadband communication and signal processing,the requirements for data converters which are the bridge between digital signals and analog signals are increasing.High-performance ADCs and DACs have become the design choke point of the entire communication chip.Research and design of high-speed and high-precision DAC chips has great commercial value and academic significance.Current steering DAC not only supports extremely high sampling rate,but also has good compatibility with CMOS technology,becoming the mainstream structure of high-speed and high-precision DAC design.Based on the TSMC 65 nm 1P9M CMOS process,this paper designs a 12-bit current steering DAC with sampling rate of 1.25 GHz.The DAC core adopts a segmented decoding structure,the 4-bit MSB are decoded by a thermometer,and the DEM is used to randomize it,and the 8-bit LSB use traditional binary decoding.Considering the area and converter performance comprehensively,the above decoding method can achieve the best performance.In this design,the decoder circuit is implemented using Verilog code,which reduces the design difficulty and the chip area effectively.For the current steering DAC,the current sources and switch units are the most important part.In the current source design,the paper demonstrates the influence of current source finite output impedance,current source mismatch and switching non-ideal effects on DAC performance from theoretical analysis and formula derivation.Finally,a two-stage cascode structure which improves the output impedance of the current source and reduces the influence of the clock feedthrough effect is adopted.The current switch unit of the DAC adopts an innovative two-level eight-switch current unit and a four-channel interpolation technology to encode the decoded signal to achieve the first-level interpolation.In the switch unit module,the clock is used to further select the coded signal to achieve two-level interpolation,and then output a high-frequency sampling signal of 1.25 GSPS to improve the dynamic performance of the DAC,and use multi-level interpolation to increase the DAC rate to make it low Under the clock frequency and low-frequency input signal,high-rate output is realized.The working principle of the new switch unit is introduced in detail through specific circuit and timing analysis.In the case of high frequency,in order to ensure the output impedance of the current source,the optimized current source unit reduces the influence of the current source output impedance with frequency changes.In this paper,the design,simulation and test of all overall circuit adopt Cadence's fully customized analog IC design platform.The output voltage swing is 1V and the full-scale current is 20 mA in the case of a load of 50?.The output SFDR can achieve 65 dB at sampling rate of 1.25 GHz.The Virtuoso tool in the Cadence environment is used to draw the layout.Comprehensive consideration of various adverse factors that may occur in the design process,by optimizing the topological structure of the current source array to improve the matching accuracy,the layout of the DAC is completed,and the expected technical index requirements are achieved.