Research On The Key Techniques Of 8-10bit,20GS/s-5GS/s Time Domain ADC

The analog-to-digital converter is one of the indispensable parts of electronic system,and its performance often restricts the application of the whole system.Because the performance of ADC implemented by traditional voltage-domain method depends heavily on high-precision analog circuit,the application range is gradually restricted under the condition that the power supply voltage and intrinsic gain are decreasing along with the technology improvement.On the contrary,time-domain ADC,as a new method,has attracted much attention due to its good process compatibility.At the same time,with the development of communication technology towards high frequency,the design of high-speed ADC has become the key to breakthrough.To solve these problems,this paper studies the system architecture and design method of high-speed time-domain ADC.In this paper,the voltage to time converter(VTC)and time to digital converter(TDC)used in time-domain ADC are described from the system point of view,and a VTC with high bandwidth and high dynamic range and a TDC with high resolution and low jitter are proposed to solve the problems of limited input range and low time resolution in existing circuits.Then,the time-interleaved method to improve the sampling rate of ADC is studied.The DC offset,gain mismatch and clock skew error between different channels in timeinterleaved ADC are discussed in detail.On this basis,the specific mismatch correction algorithm is given.Next,a scheme is proposed to realize the synchronous reconfiguration of ADC bit and sample rate in time domain.By adding a binary weighted current source into VTC,the ADC has the ability of working in 20-GS/s,8-bit mode,10-GS/s,9-bit mode and5-GS/s,10-bit mode.Finally,other key modules,such as high-speed sample and hold circuit,time amplifier and clock generation circuit,are introduced and simulated in detail.Based on the above,an 8-10 bit,20GS/s-5GS/s time-domain time-interleaved reconfigurable ADC is designed.The simulation results show that the maximum SNDR and SFDR of the ADC are 40.73 d B and 46.22 d B respectively at 20GS/s sampling rate,and the peak to peak values of DNL and INL are-0.451/-0.853 LSB respectively.The maximum SNDR and SFDR are 45.86 d B and52.57 d B respectively at 10GS/s sampling rate,and the peak to peak values of DNL and INL are +0.297/-0.947 LSB respectively.The maximum SNDR and SFDR are +0.297/-0.947 LSB respectively at 5GS/s sampling rate,and the peak to peak values of DNL and INL are +0.880/-1.005 LSB,respectively.The chip is fabricated in SMIC 40 nm 1P8M process,with an overall area of 1210?m*1382?m.