Research On Key Technologies Of The Ultra High Speed Time Domain Analog-to-Digital Converter

High-speed Analog-to-Digital Converters(ADC)are essential components in ever-increasing data rate transceiver.The ever-growing demands for high-bandwidth communications continuously push ADCs to operate at high sampling rates and low signal-to-noise ratio(SNR).The large-scale time-interleaved architecture based on single-channel ADCs is an effective means of achieving ultra-high sampling rates.As a time-interleaved architecture for multi-module parallel systems,its key metrics for high bandwidth and linearity are closely related to the effectiveness of sampling,the accuracy of interleaved clocks,single-channel efficiency,and area,among other performance aspects.This thesis is oriented toward the application of high-speed data transmission systems,and it explores the architectural and critical circuit technologies of high-speed time-domain ADC.A significant emphasis is placed on essential technologies,including the high-precision and low-noise generation and distribution of sampling clocks,high-efficiency and highly integrated single-channel ADCs,high linearity,high-bandwidth input drivers,and hierarchical sampling.Finally,this work also includes the chip-level testing and validation of relevant ADC circuits.This thesis analyzes the primary sources of clock noise and jitter and investigates the architecture of wideband Voltage-Controlled Oscillators(VCOs)to achieve configurable sampling rates.Addressing the limitations of the Frequency Tuning Range(FTR)in traditional architectures,the thesis examines key techniques for expanding the FTR.It provides a comparative analysis of the advantages and disadvantages of corresponding architectures based on their principles.The thesis introduces an FTR expansion technique based on a dual-mode tunable inductor architecture.A single-core VCO architecture is fabricated in a 65nm CMOS process,with chip testing and validation results demonstrating practicality.The phase noise of the VCO measured at a 1MHz frequency offset,after dividing by 1/2,is-114.7d Bc/Hz at the 18.49GHz output and-112.23d Bc/Hz when measured at the 12.52GHz output.The 1/f~3 phase noise angle falls within the range of 560 to 820KHz.Additionally,by incorporating the fine-tuning mode of a dual-mode inductor,a temperature-compensation calibration algorithm for the VCO has been implemented.The minimum adjustment frequency step is only 177MHz.To enhance the power efficiency of the clock source,the thesis introduces a low-voltage,low-power active dual-loop Phase-Locked Loop(PLL)chip.This chip includes an active loop filter with a reset feature,significantly reducing the current mismatch requirements of the fully differential charge pump,thereby effectively suppressing the degradation in clock jitter performance caused by reference clock spurs.Based on the 28nm CMOS process,simulation results indicate that at a supply voltage of0.7V,the frequency output range is 27.4-32.5GHz,with high-frequency phase noise at-101.3d Bc/Hz@1MHz and low-frequency phase noise at 100.5d Bc/Hz@1MHz.The power consumption is only 12.7m W,with the core area is 0.096mm2.High-performance single-channel ADCs are crucial for large-scale time-interleaved architectures.The speed,power efficiency and integration have great influence on design complexity,power supply stability,sampling network accuracy and bandwidth,respectively.Time-domain ADCs,known for their strong digital characteristics,can fully benefit from advanced integrated circuit processes.This thesis addresses performance limitations in traditional time-domain ADC architectures due to variations in Process,Voltage,and Temperature(PVT).Based on fully differential time units and current reference,a Voltage-to-Time Converter(VTC)and TDC gain error adaptive technology is introduced,here.The prototype is fabricated in a 28nm CMOS process with a supply voltage of 0.9 V,a 4GS/s 6-bit single-channel mixed-domain architecture ADC was designed and implemented.Test results indicate that the SNDR at the Nyquist frequency reaches 30.61d B.TheΔSNDR remains under 0.76d B across a temperature range of-20°C to 100°C.With a 5.5%variation in the power supply voltage,theΔSNDR is only 1.07d B.At a standard supply voltage of0.9V,the ADC core power consumption is 8.1m W,the Fo M_W value is 73.1f J/conv.-step,and the chip area is 0.0099mm2.This thesis addresses the limitation of the minimum time quantization unit caused by jitter accumulation in TDC quantization delay chains.It introduces a passive transmission-based phase-interleaved time quantization technique,achieving a minimum time quantization of 416.6fs.The TDC provides stable PVT characteristics as the wave velocity in passive transmission lines is solely dependent on parasitic parameters.Designed and implemented a 5GS/s 8-bit single-channel two-stage mixed-domain ADC using the 28nm CMOS process.Measurement results show an SNDR of 38.04d B at Nyquist frequency,withΔSNDR of 0.34d B over a temperature range of-25°C to 125°C.Under a 5%power supply voltage variation,ΔSNDR is 0.74d B.The ADC’s core power consumption is 19.8m W,with a Fo M_W value of 60.7f J/conv.-step.The active area of the ADC is 0.012mm2,and the area of the two pairs of differential transmission lines is105μm×706μm.The thesis addresses the design challenges in large-scale time-interleaved ADC architectures.It presents the design and implementation of a 16-channel time-interleaved ADC with a32GS/s sampling rate and 8-bit quantization accuracy using a two-stage hierarchical front-end sampling network.To mitigate the impact of common-mode mismatches and channel-specific offset voltages within the time-interleaved architecture,the thesis proposes a single-channel internal error voltage self-testing and independent analog calibration approach.To reduce the impact of parasitic capacitance and resistance on signal bandwidth and simplify clock design in time-interleaved ADCs,a single-channel architecture using phase interpolation techniques has been developed.It implements a two-stage cascaded structure for a 2GS/s 8-bit time-domain ADC.To address power consumption and high-frequency clock synchronization challenges in high-speed data serialization,a value serialization technique based on multi-phase sampling clock reuse is proposed,effectively solving on-chip high-speed clock transmission and phase alignment issues.Utilizing the 28nm CMOS process,layout implementation,and post-simulation verification,the chip achieved a worst-case post-PVT simulated SNDR of 41.9d B at Nyquist frequency.A single-channel time-domain ADC,with compact dimensions of 23.4μm×82.6μm,consumes 7.02m W.The ADC core area is 0.113mm2,and the Fo M_W value is 34.52f J/conv.-step...