Research On Key Technologies Of Time-interleaved Analog-to-digital Converter

As the bridge between analog circuits and digital circuits,analog to digital converter has been widely used in communication systems,computer science,instruments and many more.After decades of research in academia and industry,the development of ADCs has made significant progress,with their increased speed and accuracy.However,the performance of classical ADC's structures is approaching the current technological limit for the slowdown of Moore's law.Time-interleaved ADCs use multiple channels to work in parallel to realize the doubling of the conversion speed of the overall system,which is an important direction to break the speed bottleneck of ADC.However,the performance of this structure is severely constrained by the mismatches between internal sub-ADCs.Among them,the sampling time mismatch between channels is the main factor that restricts the high-speed performance of the time-interleaved ADC.Compared with other mismatches between channels,sampling time mismatch calibration is more complicated and difficult.What's worse,the back-end calibration algorithm usually imposes constraints on the system input,made itself a hot issue in current academic research.In addition,the upper limits of the bandwidth and linearity of the pre-stage sample-and-hold circuits,especially the performance of the high-speed bootstrapped switches and input buffers,restrict the speed and accuracy of the time-interleaved ADCs.The requirements of these modules increase synchronously with the improvement of the corresponding index of the system,which are critical issues of the analog design in high-performance time-interleaved ADCs and have been more and more concerned by academia in recent years.For sampling time mismatches in the system,this paper summarizes the existing skew correction methods systematically and proposes a new kind of skew background correction method.The proposed method utilizes an extra channel as the sampling time reference and the arithmetic relevant to accumulation and comparison of the sampling error of the input in the time domain.The sampling clock phase of each channel in the time-interleaved ADC is turned in negative feedback logic.Compared with those traditional background skew calibration methods,the proposed method can support any input signals and could be easily extended to any number of interleaved channels.The constraints on the performance of the front-end input driver on account of the requirements of high speed and high precision of time-interleaved ADC,a wideband high-linearity buffer is proposed in low power.This buffer is based on the source follower and its linearity is improved with front-end capacitor and input-bootstrap structure.For the load capacitor of 4pF and the input swing of 600mV in single-ended,the bandwidth of the differential driver could expand to 2.5GHz with the gain compression less than 10%.Compared with typical source followers,the linearity of this design raised 15dB.To meet the sampling rate requirements of the system,a new type of bootstrapped switch presented with high performance.This switch decreases the on-resistance of the bootstrapped loop with level shift structure,which reduces the minimum conduction time of the bootstrapped switch,realized its high-speed applications.With a load capacitor of 2pF,the sampling speed of this bootstrapped switch could achieve 5GHz with its accuracy of 12bit,raised up 150%compared with the typical structure.A 2GS/s 12bit ADC with 8 pipelined ADCs interleaved is designed with the above techniques.The front-end adopts a two-level sub-sampling architecture with the input buffer and high-speed bootstrapped switches proposed used in the fast pre-stage sample-and-hold module.The skew between channels is calibrated with the proposed skew calibration method.The post-simulated results show that the SNDR of the time-interleaved ADC has been improved 17dB after calibration.The SNDR of the system is higher than 60dB with the input in the first Nyquist zone.To verify the proposed sampling time mismatch correction method between channels,a 625MS/s 12bit two-channel time-interleaved ADC is implemented in the 40nm CMOS process.The test results show that the SFDR and SNDR of the interleaved system improved by 17dB and 10dB,respectively,the corresponding ENOB raises by about 1.1bit,proving the practicability and effectiveness of the method.