| With the advent of the digital information era,digital information processing technology has made unprecedented advances,while signals in the natural world are almost always in analog form.Therefore,as a bridge between the natural world and the human digital world,Analog to Digital Converters(ADCs)play a crucial role in various digital communication systems.However,with the development of wireless communication,traditional ADCs have shown limitations in performance.TimeInterleaved(TI)ADCs,which use time-interleaved technology and work through multiple channels alternately,can significantly increase the sampling rate of ADCs while ensuring conversion accuracy.Compared to other architectures,TI ADCs lead in the high-speed field,especially those that use SAR ADC as sub-channels which have significant advantages in power consumption.This thesis focuses on the research and design of time-interleaved SAR ADC,and proposes key modules and calibration methods.For single-channel SAR ADC,this article optimizes in multiple aspects: adopting a lower energy consumption conversion strategy to reduce DAC conversion power consumption;increasing substrate bias effect elimination structure to improve sampling switch linearity;improving high-speed dynamic comparators to obtain lower power consumption and noise;adopting adaptive sampling asynchronous SAR logic to reduce time interval waste.For time-interleaved SAR ADC,this article analyzes the working principle and main mismatch problems,and proposes a calibration scheme based on MATLAB LMS algorithm.Finally,an 8-channel12-bit 800MS/s time-interleaved SAR ADC circuit is successfully designed using 65 nm standard CMOS process,where the sub-ADC is a 12-bit 100MS/s SAR ADC.These optimization measures can improve the accuracy and stability of the ADC and have important practical significance in actual applications.The design includes circuit design,layout drawing,calibration algorithm research,and simulation verification of time-interleaved multi-channel SAR ADC,with a circuit core area of only 728 um × 709 um.At Nyquist input frequency and tt process corner,the pre-simulation result of a single channel shows: SNDR is 71.1d B,SFDR is 79.9d B,ENOB is 11.53 bit,and power consumption is 1.92 mW;the layout simulation result of a single channel shows: SNDR is 66.1d B,SFDR is 72.9d B,ENOB is 10.69 bit,and power consumption is 2.13 mW;The pre-simulation result of the 8-channel interleaved SAR ADC shows: SNDR is 70.5d B,SFDR is 83.6d B,ENOB is 11.41 bit,and power consumption is 17.81 mW.The layout simulation result of the 8-channel interleaved SAR ADC shows: SNDR is 64.9d B,SFDR is 73.9d B,ENOB is 10.48 bit,and power consumption is 19.42 mW... |
